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Method for reducing coefficient of thermal expansion in chip attach packages

a technology of thermal expansion and chip, applied in the field of method for reducing the coefficient of thermal expansion in the chip, can solve the problems of warpage within the package, chip cracking, and often expensive process steps, and achieve the effects of lowering the cte, lowering the cte, and lowering the

Inactive Publication Date: 2005-01-11
IBM CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention provides a simple and inexpensive way to make a reduced CTE laminate that can be drilled and used in circuitized structures. The laminate is made up of a resin, curing agent, woven cloth, and non-woven quartz or glass mat. The method involves sandwiching the non-woven mat between two layers of pre-cured resin and then reflowing the resin into the mat. This laminate has a reduced CTE, which makes it useful in applications where temperature stability is important.

Problems solved by technology

The differential expansion can cause warpage within these packages, including flip chip attach packages.
This warpage can fatigue chip attach joints and also cause chip cracking.
Attempts have been made to reduce the warpage of the package; however they require additional, often expensive process steps.
Copper-invar-copper is expensive and difficult to drill.
Molybdenum is expensive, tough to drill, and hard to etch with conventional etchants.
However, encapsulants and top stiffeners add extra processing steps, cost, complexity and they occupy additional space.
However, dielectric which employs woven quartz cloth is thick and heavy which limits the usefulness of the prepreg.
Furthermore, laminates made with such quartz prepreg are difficult to drill due to the hardness of the quartz and the thickness of the quartz yarn bundles.

Method used

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  • Method for reducing coefficient of thermal expansion in chip attach packages
  • Method for reducing coefficient of thermal expansion in chip attach packages
  • Method for reducing coefficient of thermal expansion in chip attach packages

Examples

Experimental program
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Effect test

example 1

Prepreg was fabricated to provide a prepreg having about 60% by weight epoxy resin, 0.1% by weight curing accelerator 2-methyl imidizole and 40% by weight E-glass 1080, and b-stage cured to about 20 to 30%. Next, a multilayered structure was assembled which comprised a layer of copper sheet, a first layer of prepreg atop the copper, a second layer of prepreg atop the first layer of prepreg, a layer of non-woven quartz mat, a third and fourth layer of prepreg and finally a second layer of copper sheet. The non-woven quartz mat was about 0.004 inches thick before lamination, had a weight per unit area of about 17 g / m2 and was obtained from Technical Fiber Products Company. The multilayered structure was then vacuum laminated in a Wabash lamination press, at 185° C. for about 120 minutes at around 750 psi, to provide a reduced CTE laminate, in this case a laminate core. The copper layers on the outside of the core were then etched to form the circuit features using conventional techniq...

example 2

A reduced CTE laminate structure was made as in example 1, except that the core lacked a non-woven mat. Instead a non-woven quartz mat was employed between the fifth and sixth prepreg layers, and between the seventh and eight prepreg layers, so that 2.3% rather than 1.2% of the laminate structure was quartz non-woven mat. The resulting composite structure had a total thickness of about 26.2 mils.

example 3

A reduced CTE laminate structure was made as in example 1, except that a non-woven quartz mat was also employed between the fifth and sixth prepreg layers, and between the seventh and eight prepreg layers, so 3.4% rather than 1.2% of the laminate was quartz non-woven mat. The resulting laminate structure had a total thickness of about 26.5 mils.

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Abstract

A simple, inexpensive, drillable, reduced CTE laminate and circuitized structures comprising the reduced CTE laminate, is provided. One embodiment of the reduced CTE laminate comprises: from about 40% to 75%, preferably from about 55% to 65%, by weight resin; from about 0.05% to 0.3%, preferably from about 0.08% to 0.10%, by weight curing agent; from about 25% to 60%, preferably from about 30% to 40%, by weight, woven cloth; from about 1% to 15%, preferably from about 5% to 10%, by volume, non-woven quartz mat. The method for making reduced CTE laminate and laminate structures comprises the following steps: providing non-woven quartz mat; providing a prepreg, preferably B-stage cured to not more than about 40%, preferably not more than 30% of full cure; sandwiching the non-woven quartz mat between two layers of prepreg, and reflowing the resin of the prepreg into the quartz mat.

Description

The presence of different materials within a chip attach package, leads to different coefficients of thermal expansion within the package. The differential expansion can cause warpage within these packages, including flip chip attach packages. This warpage can fatigue chip attach joints and also cause chip cracking.Attempts have been made to reduce the warpage of the package; however they require additional, often expensive process steps. Material shaving a low coefficient of thermal expansion, like molybdenum, combinations of metals like copper-invar-copper, or other exotic organic reinforcements such as Kevlar, have been employed in packages to reduce the coefficient of thermal expansion. Kevlar, however, absorbs moisture. Copper-invar-copper is expensive and difficult to drill. Molybdenum is expensive, tough to drill, and hard to etch with conventional etchants.Attachments such as stiffeners or encapsulants on top of the chip are often employed to counteract warpage. However, enc...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): B32B5/28B32B5/22H05K1/03
CPCB32B5/28H05K1/036H05K1/0366Y10T29/4913H05K2201/0293H05K2201/068H05K2201/029Y10T442/3537Y10T442/3659Y10T442/3585Y10T442/2361Y10T442/3602Y10T442/2992Y10T442/3577Y10T442/3569B32B5/02B32B2260/023B32B5/26B32B2553/00B32B2262/101B32B2260/046B32B2305/20
Inventor BLUMBERG, LAWRENCE ROBERTJAPP, ROBERT MAYNARDRUDIK, WILLIAM JOHNSUROWKA, JOHN FRANK
Owner IBM CORP
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