Semiconductor device and its making method

A manufacturing method and semiconductor technology, which are applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of affecting the electrical performance of the device, low corrosion selectivity, and erosion of the silicon oxide layer 130, and avoid the sidewall spacing. The effect of the depression under the object

Active Publication Date: 2009-07-22
SEMICON MFG INT (SHANGHAI) CORP +1
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Problems solved by technology

However, since the material of the self-alignment barrier layer 160 is silicon rich oxide (SRO) with a high density, and the material of the silicon oxide layer 130 in the sidewall spacer is LTO, the texture is relatively loose, and hydrogen When hydrofluoric acid is corroded, the corrosion selectivity of hydrofluoric acid to the above two materials LTO and SRO is low, about 1:5
Therefore, when hydrofluoric acid is used to remove the self-alignment barrier layer 160, it is very easy to corrode the silicon oxide layer 130, resulting in the formation of recesses 200 and 200' under the sidewall spacers, which affects the electrical performance of the device.

Method used

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  • Semiconductor device and its making method
  • Semiconductor device and its making method
  • Semiconductor device and its making method

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Embodiment Construction

[0034] In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0035] In the following description, specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention can be implemented in many ways other than those described here, and those skilled in the art can make similar extensions without departing from the connotation of the present invention. Accordingly, the invention is not limited to the specific implementations disclosed below.

[0036] The semiconductor device and its manufacturing method provided by the invention are especially suitable for semiconductor devices with a feature size of 65nm or below and its manufacturing. The semiconductor device is not only a MOS transistor, but also a PMOS transistor and an NMOS tra...

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Abstract

The invention discloses an semiconductor apparatus and a method of manufacturing the same, wherein the method comprises the following steps of: providing a semiconductor substrate which forms a grid on the surface of the semiconductor substrate; forming a high dielectric constant oxide layer which covers the surface of the substrate and the grid; forming a silicon nitride layer which covers the oxide layer; etching the oxide layer and the nitride layer to form a sidewall spacer; forming a source and a drain between the substrates of the two sides of the sidewall spacer; forming a self-aligned barrier layer which covers the substrate, the sidewall spacer and the surface of grid; utilizing the self-aligned barrier layer as the mask to form a metal silicide on the surface of the grid, source and drain; stripping the self-aligned barrier layer. The invention can avoid the dent of the lower part of the sidewall spacer effectively during the process of utilizing self-aligned technology to form metal silicide.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a metal oxide semiconductor (MOS) device and a manufacturing method thereof. Background technique [0002] Metal silicide plays a very important role in VLSI / ULSI device technology. The self-aligned silicide (Salicide) process has become one of the key manufacturing processes for forming metal silicide in ultra-high-speed CMOS logic large-scale integrated circuits recently. It offers many benefits to the fabrication of high-performance logic devices. This process simultaneously reduces the sheet resistance of the source / drain and gate electrodes, reduces contact resistance, and shortens gate-related RC delays. In addition, it also allows increased device integration by increasing circuit packaging density. In the self-alignment technology, a reaction product of a metal and a semiconductor such as silicon (Si) is formed on the source and drain regions of a M...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L21/28H01L29/78H01L29/423H01L29/43
Inventor 张海洋韩秋华杜珊珊韩宝东
Owner SEMICON MFG INT (SHANGHAI) CORP
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