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Semiconductor device and method for fabricating the same

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., can solve the problems of increased resistance of the diffusion layer, increased resistance of thin lines, and reduced width, so as to prevent the increase of resistance Large, the effect of preventing the increase in the resistance of silicide thin wires

Inactive Publication Date: 2009-08-19
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0015] First, the surface area of ​​the diffusion layer 11 formed by source / drain (S / D) implantation becomes smaller, resulting in an increase in the resistance of the diffusion layer
In particular, when the silicide layer 12 is formed on the semiconductor substrate 1 and used as a thin line resistor, the width of the silicide layer 12 is reduced due to the sidewall 10 formed at the step portion of the first STI region 2 of the storage unit 100. becomes smaller, thus resulting in an increase in the thin-wire resistance

Method used

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  • Semiconductor device and method for fabricating the same
  • Semiconductor device and method for fabricating the same
  • Semiconductor device and method for fabricating the same

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no. 1 approach

[0043] refer to figure 1 The semiconductor device according to the first embodiment of the present invention will be described.

[0044] Such as figure 1 As shown, the semiconductor device according to the first embodiment has a storage unit 100 and a CMOS unit 200 formed on a semiconductor substrate 51 made of, for example, p-type silicon (Si), wherein the storage unit 100 includes an ONO film capable of accumulating charges. 56 storage transistors, and the CMOS unit 200 includes transistors constituting peripheral circuits of the storage unit 100 and performs logic operations. Here, the ONO film 56 is formed by sequentially forming, for example, a lower silicon oxide layer 56a with a thickness of 5nm, a silicon nitride layer 56b with a thickness of 10nm as a material for substantially accumulating charges, and an upper silicon oxide layer 56c with a thickness of 15nm.

[0045] In the storage unit 100, a first shallow trench isolation (STI) region 52 for insulating and se...

no. 2 approach

[0061] Below, refer to Figure 5 A semiconductor device according to a second embodiment of the present invention will be described. exist Figure 5 in, right with figure 1 Components with the same symbols in , are given the same symbols, and descriptions are omitted.

[0062] In the semiconductor device of the second embodiment, the diffusion layer 61 formed on the semiconductor substrate 51 of the first embodiment is formed as a silicide layer 62 silicided.

[0063] silicide layer 62, such as Figure 6 As shown in (a), it is formed in the following manner, namely: in the first embodiment Figure 4 In the step shown in (b), a metal film containing, for example, titanium (Ti), cobalt (Co) or nickel (Ni) is deposited on the diffusion layer 61 by vapor deposition, and heat treatment is performed on the deposited metal film. The silicidation process silicides each diffusion layer 61 to become a silicide layer 62 .

[0064] Even after this silicidation step, the height of t...

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Abstract

A semiconductor device includes a memory section formed at a semiconductor substrate and including a first transistor having an ONO film that can store charges between the semiconductor substrate and a memory electrode and a first STI region for isolating the first transistor, and a CMOS section formed at the semiconductor substrate and including a second transistor having a CMOS electrode and a gate dielectric and a second STI region for isolating the second transistor. The height of the top surface of the first STI region is set equal to or smaller than the height of the top surface of the second STI region.

Description

technical field [0001] The present invention relates to a semiconductor device having a storage (memory) portion and a logic (CMOS) portion on a semiconductor substrate, and a method of manufacturing the same, wherein the memory portion has an ONO (upper silicon oxide layer / silicon nitride layer / lower silicon oxide layer) as a gate insulating film. layer) film. Background technique [0002] A semiconductor device in which a memory portion and a CMOS portion are mixedly mounted on a semiconductor substrate and an ONO film is used as a gate insulating film of a memory transistor constituting the memory portion is becoming more and more important as the miniaturization of elements progresses. [0003] Below, refer to Figure 7 (a)~7(c) and Figure 8 (a)~ Figure 8 (c) A conventional semiconductor device having a mixed storage unit and a CMOS unit and a method of manufacturing the same will be described. [0004] First, if Figure 7 As shown in (a), a first shallow-trench iso...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/105H01L27/115H01L21/8239H01L21/8247H10B69/00H10B99/00
CPCH01L27/1052H01L21/823878H01L29/792H01L27/11573H01L27/105Y10S438/954H01L27/11568H10B43/40H10B43/30
Inventor 高桥信义岩本知士野吕文彦荒井雅利
Owner PANASONIC CORP