Embedded type chip packaging structure

Abstract

The invention relates to a chip encapsulation structure with an embedded type. The encapsulation structure includes a double-sided substrate, an intermediate dielectric layer, a first metal layer arranged on a first surface of the intermediate dielectric layer, a second metal layer arranged on a second surface of the intermediate dielectric layer, a recess which is formed in the second metal layer and the intermediate dielectric layer, and the bottom of which is the first metal layer; a chip which is positioned in the recess and the bottom of which is in thermal touch with the first metal layer; a storey adding material layer which covers on the second metal surface and an active surface of the chip and is filled into a clearance between the side of the chip and the interlayer dielectric layer; and at least an interconnection tie line layer which is formed on the storey adding material layer and electrically connected with a connection pad arranged on the active surface of the chip through at least a contact watt plug.

Description

Technical field [0001] The present invention relates to the field of packaging technology, in particular to an embedded chip packaging structure with better heat dissipation efficiency. Background technique [0002] With the development of integrated circuit technology, the design of high-performance microprocessor packages has become increasingly challenging. Future microprocessors will have more signal pins; the control requirements for pin impedance and crosstalk between pins will be more stringent; greater power consumption and better heat dissipation. For microelectronic packaging, its electrical performance and thermal management are two major challenges. Electrically, the package must ensure the signal integrity and the operating frequency of the semiconductor device to the greatest extent. This task is usually difficult to complete due to the excessive total inductance introduced into the device-package-motherboard in the package design. On the other hand, packaging is ...

AI Technical Summary

Problems solved by technology

[0010] From the current technical point of view, BBUL is prone to defects in the surface layer wiring process. For example, tape support is required in the process. After the tape 14 is removed, the connection pad 22 on the active surface 20a of the chip 20 may occur. Residual glue problem, which will seriously affect the good rate of finished products

Once the yield of finished products is affected, the cost of processor products designed with BBUL packaging technology will far exceed the current processor products

[0011] In addition, due to the difference in coefficient of thermal expansion (CTE) between the semiconductor chip, the filler 30 and the base material 10, cracking of the wiring may be caused when the surface layer wiring is performed.

Furthermore, the heat dissipation performance of the package formed by the known BBUL packaging technology needs to be improved.

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