Nonvolatile semiconductor memory device

A non-volatile storage and storage device technology, applied in the field of non-volatile semiconductor storage devices, can solve problems such as high write voltage, and achieve the effects of improving water resistance, inhibiting degradation, and improving charge retention characteristics

Inactive Publication Date: 2007-09-26
SEMICON ENERGY LAB CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] In summary, existing nonvolatile memories require high write voltages

Method used

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  • Nonvolatile semiconductor memory device
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  • Nonvolatile semiconductor memory device

Examples

Experimental program
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Embodiment 1

[0134] In this embodiment, an example of a nonvolatile semiconductor memory device will be described with reference to the drawings. Here, a case is shown in which a nonvolatile memory element constituting a memory portion and elements such as transistors constituting a logic portion provided in a nonvolatile semiconductor memory device are formed simultaneously with the memory portion. On the same substrate and perform control of the memory part, etc.

[0135] First, an equivalent circuit of the memory portion of the nonvolatile semiconductor memory device is shown in FIG. 8 .

[0136] In the memory section shown in this embodiment, a plurality of memory cells having selection transistors and nonvolatile memory elements are provided. In FIG. 8, one memory cell is formed by the selection transistor S01 and the nonvolatile memory element M01. Also, like this, the selection transistor S02 and the nonvolatile memory element M02, the selection transistor S03 and the nonvolatile ...

Embodiment 2

[0184] In this embodiment, a case where a plurality of nonvolatile memory elements are provided on one island-shaped semiconductor layer in the structure shown in Embodiment 1 above will be described with reference to the drawings. Note that the same symbols are used for the same parts as those of the above-described embodiment, and descriptions thereof are omitted. FIG. 37 shows a plan view, and FIGS. 38A and 38B show cross-sectional views along lines E-F, G-H in FIG. 37 .

[0185] In the nonvolatile semiconductor memory device shown in this embodiment, there are provided island-shaped semiconductor layers 200a and 200b electrically connected to bit lines BL0 and BL1, respectively, and a plurality of A non-volatile memory element (see FIGS. 37 and 38). Specifically, in the semiconductor layer 200a, a NAND cell 202a including a plurality of nonvolatile memory elements M0 to M31 is provided between the selection transistors S01 and S02. Furthermore, in the semiconductor layer...

Embodiment 3

[0190] In this embodiment, a method of manufacturing a semiconductor device different from that of Embodiment 1 described above will be described with reference to the drawings. Note that the same symbols are used for the same parts as those of the above-described embodiment, and descriptions thereof are omitted. Note that in FIGS. 22A to 24B , A-B and C-D show thin film transistors provided in the logic part, E-F show nonvolatile memory elements provided in the memory part, and G-H show thin film transistors provided in the memory part.

[0191] First, the steps up to FIG. 18C are performed in the same manner as in the above-described embodiment, and then the resist 122 is removed, and the semiconductor layers 104, 106, and 110, the first insulating layer 116 formed on the semiconductor layer 108, and the charge storage layer 121 are covered. The second insulating layer 128 is formed in a stacked structure with the charge storage layer 125 (see FIG. 22A ).

[0192] Next, a r...

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PUM

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Abstract

It is an object to provide a nonvolatile semiconductor memory device having excellent writing property and charge-retention property. A semiconductor layer including a channel forming region between a pair of impurity regions which are formed to be apart from each other is provided. In an upper layer portion thereof, a first insulating layer, a floating gate, a second insulating layer, and a control gate are provided. The floating gate has at least a two-layer structure, and a first layer in contact with the first insulating layer preferably has a band gap smaller than that of the semiconductor layer. Furthermore, by setting an energy level at the bottom of the conduction band of the floating gate lower than that of the channel forming region of the semiconductor layer, injectability of carriers and a charge-retention property can be improved.

Description

technical field [0001] The present invention relates to a nonvolatile semiconductor memory device capable of electrical writing, electrical reading, and electrical erasing, and a method of manufacturing the same. The present invention particularly relates to the structure of the floating gate in the nonvolatile semiconductor memory device. Background technique [0002] The market for nonvolatile memories capable of rewriting data electrically and storing data even after power is cut off is expanding. A nonvolatile memory is characterized in that it has a structure similar to a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and is provided with a region capable of storing charges for a long time on a channel formation region. The charge storage region is formed on an insulating layer and is insulated from the surroundings, so it is also called a floating gate. The floating gate is electrically insulated and separated from the surroundings ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/115H01L29/788H01L29/49H01L29/423
CPCG11C16/0433H01L27/11546G11C16/0483G11C16/0416H01L29/7881H01L27/12H01L27/11526H01L27/1214H01L27/115H10B41/49H10B41/40H10B69/00
Inventor 山崎舜平浅见良信高野圭惠古野诚
Owner SEMICON ENERGY LAB CO LTD
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