High voltage P type SOI MOS transistor

Abstract

A high voltage P type silicon-on-insulator metal oxide semiconductor pipe comprises a semiconductor substrate. An insulator buried oxide layer, a P type doped semiconductor area and an N well area are arranged on the semiconductor substrate, while a field oxide layer, a metal layer, a gate oxide, a polysilicon gate and an oxide layer are arranged on the surface of the device. The metal oxide semiconductor pipe is characterized in that a barrier oxide layer is arranged on a buried oxide layer and is positioned below the gate oxide; a channel area is formed between the barrier oxide layer and gate oxide; an N type inversion layer is arranged in the P type doped semiconductor area and is positioned on the lower surface of the field oxide layer between a P type drain area and a P type source area. With such a structure, electrons induced on an interface where the P type doped semiconductor area is connected with the buried oxide layer gather on the bottom of the P type doped semiconductor area, greatly increasing the charge density at the interface, therefore, a thinner buried oxide layer can bear higher vertical breakdown voltage.

Description

Technical field: [0001] The present invention relates to the field of power semiconductor devices, and more specifically, relates to a structure of a silicon-on-insulator metal oxide semiconductor (SOI LDMOS) suitable for high-voltage applications. Background technique: [0002] Since the device made of silicon-on-insulator material can realize full dielectric isolation, its parasitic capacitance and leakage current are small, and the driving current is large, so it is very suitable for manufacturing power integrated circuits and devices. In order to make silicon-on-insulator devices work better, it is an important research topic to improve the breakdown voltage of silicon-on-insulator devices. As we all know, the withstand voltage of a silicon-on-insulator power device depends on the minimum of its lateral withstand voltage and vertical withstand voltage. The lateral withstand voltage of the device can be achieved by using bulk silicon junction termination technologies such...

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Problems solved by technology

However, it makes most of the buried oxide layer have a large thickness, which is not conducive to the heat dissipation of the device, and also reduces the bonding strength. In addition, the etching of a large number of grooves also brings the complexity of the entire manufacturing process.

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