Method for repairing and etching polysilicon

Abstract

The invention discloses a method for repairing and etching polysilicon, which belongs to the technical field of microelectronics manufacturing. The method provided by the invention is used for repairing and etching the polysilicon forming a control grid in an EEPROM and is characterized by only adopting a mixed chemical gas of O2 and CF4 for plasma etching. The etching method is a chemical etchingand has a extremely low substrate silicon etching speed, thereby avoiding damaging a pn junction between a source electrode and a substrate and a pn junction between a drain electrode and the substrate and consequently ensuring the reliability of the EEPEOM device and improving the yield of product.

Description

technical field [0001] The invention belongs to the technical field of microelectronics manufacturing, and in particular relates to a method for repairing and etching polysilicon. Background technique [0002] Electrically Erasable Programmable Read-Only Memory (EEPROM) is a non-volatile memory whose gate structure has a floating gate (Polysilicon) material and a control gate (Control Gate), floating gate and control gate There is a dielectric layer structure of silicon oxide-silicon nitride-silicon oxide (Oxide-Nitride-Oxide) between them, which is used to trap charges. [0003] In the current fab, the main manufacturing process of the gate of EEPROM is as follows: figure 1 As shown, after the channel doping of EEPROM is preliminarily completed, the first layer of gate dielectric layer is formed by patterning, and further, in step S11, the first layer of polysilicon is deposited on the first layer of gate dielectric, and the first layer of polysilicon is patterned and etch...

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Problems solved by technology

[0004] However, in the restoration etching process of step S16, the method of plasma physical bombardment is currently mainly used for etching, and the etching reaction chamber is mainly filled with Ar 2 gas and a small amount of O 2 、CF 4 , Ar plasma is formed in the chamber, and Ar ions bombard the surface under the action of electric field acceleration. Since the surface after silicon oxide is etched in step S15 is mainly a silicon substrate, Ar is an inert atom, so it will not chemically etch with surface substances. Etching, mainly through physical bombardment, etch the residual oxide dielectric and polymer components, but we also found that this repair etching method will etch away the silicon that will be used to form the source and drain In the substrate region, the substrate silicon in the source and drain regions will be etched away by 1-15nm, so that the substrate used to form the source and drain is damaged, the pn junction between the source and the substrate, and the drain and the substrate The pn junction between may be damaged directly during the repair etch

figure 2 Shown is the electrical performance test diagram of the wafer formed after the repair etching of the prior art. The EEPROM device is formed under the 0.35um process condition, and the leakage current between the wafer substrate and the source and drain is mainly tested. A reverse bias is applied between the drain and the wafer substrate, from figure 2 It can be seen that the dots in the wafer indicate that a large leakage current has occurred between the source and drain electrodes and the wafer substrate, and the leakage current of the junction in the black area in the center of the wafer is higher than that of the junction in the surrounding gray area. The leakage current is 2 to 3 orders of magnitude larger, so this repair etching method in the prior art will seriously reduce the yield, the yield is in the range of 75% to 85%, and because of the unevenness of etching, it is unqualified The devices are mainly distributed in the central part of the wafer

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