Processing method of fuse wire on copper interconnection layer and semiconductor device thereof

Abstract

The invention discloses a processing method of a fuse wire on a copper interconnection layer and a semiconductor device thereof. The copper interconnection layer comprises a top copper interconnection layer, a middle copper interconnection layer and a bottom copper interconnection layer. The invention is characterized in that the method comprises the following steps: depositing a passivation layer on the top copper interconnection layer; patterning the passivation layer, and etching until a copper interconnection line in the top copper interconnection layer is exposed; depositing a metallic aluminum layer on the surface of the patterning passivation layer and the surface of the interconnection line of the top copper interconnection layer; pattering the metallic aluminum layer, and formingan aluminum gasket connected with the interconnection line of the top copper interconnection layer; defining the position of a fused hole on the patterning passivation layer, and etching to form the fused hole; depositing a polyimide film on the surface of the aluminum gasket, the surface of the patterning passivation layer and the bottom surface of the fused hole; and removing the polyimide filmon the surface of the aluminum gasket and on the bottom surface of the crater. The invention also discloses a semiconductor device. The method can simplify the technical manufacture procedure, and the semiconductor device can improve the electrical property and the operation speed of the device.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a fuse on a copper interconnection layer and a semiconductor device thereof. Background technique [0002] Along with the miniaturization and high integration of semiconductor devices, downscaling of internal interconnections and realization of multilayer internal interconnections have begun. In the interconnection process, a trench for interconnection patterns is formed in the intermetal dielectric layer (Intermetal Dielectric, IMD), and the interior of the trench is buried with interconnection materials, and then the interconnection material outside the trench is removed, only The interconnect material is left inside the trench. In this way, interconnect lines are formed which are buried in the IMD. Copper is increasingly used as an interconnect material because copper can achieve lower resistance than aluminum. Copper interconne...

AI Technical Summary

Problems solved by technology

[0016] It can be seen that in steps 2D and 2E of the prior art, two steps of coating photoresist are required to first expose the aluminum liner 102 and then define the fusion hole 104. If only one photoresist coating is performed, at the same time define The position of the aluminum liner and the melting hole, the etching passivation layer to expose the aluminum liner and the formation of the melting hole will be carried out at the same time, because the etching depth of the etching passivation layer to expose the aluminum liner and the depth of etching to form the melting hole are Different, so it cannot be realized by one-time photoresist coating, and the operation process is more complicated to realize

[0017] In this copper interconnect process, the etch-stop silicon nitride film has a relative permittivity of about 7, significantly greater than that of silicon oxide of about 4, which increases the relative permittivity of the entire IMD , so that the parasitic capacitance between the copper interconnect lines increases, thus causing the defect of signal delay or increased power consumption

Images