Unlock instant, AI-driven research and patent intelligence for your innovation.

N-type metal oxide semiconductor source drain implantation method

An oxide semiconductor and metal technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of increased gate oxide leakage current and high processing complexity, and achieve the effect of improving performance

Inactive Publication Date: 2011-04-06
SEMICON MFG INT (SHANGHAI) CORP
View PDF0 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0020] In order to improve the performance of NMOS, the following methods are usually adopted: 1. Reduce the thickness of the gate oxide layer, which has the disadvantage of increasing the leakage current of the gate oxide layer; 2. Use stress engineering methods to eliminate the stress of silicon dioxide. The disadvantage is that the processing complexity is higher

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • N-type metal oxide semiconductor source drain implantation method
  • N-type metal oxide semiconductor source drain implantation method
  • N-type metal oxide semiconductor source drain implantation method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0041] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0042] figure 2 The flow chart of the NMOS source-drain injection method provided by the embodiment of the present invention, such as figure 2 As shown, the specific steps are as follows:

[0043] Step 201: forming an N well, a P well, and an STI on a semiconductor substrate of a silicon wafer.

[0044] Step 202: grow a gate oxide layer and deposit polysilicon on the surface of the silicon wafer, and use photolithography and etching to form an NMOS gate structure above the N well, and form a PMOS gate structure above the P well.

[0045] Step 203: performing LDD implantation on the semiconductor substrates on both sides of the NMOS and PMOS gate structures respectively.

[0046] Step 204: Deposit silicon dioxide and silicon nitride sequentially on the surface of the silicon wafer and the sidewalls and surfaces of the NMOS and PMO...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses an N-type metal oxide semiconductor source drain implantation method, which comprises the following steps of: forming a grid structure of an NMOS (N-type metal oxide semiconductor) above an N well of a semiconductor substrate of a silicon chip; performing LDD (lightly doped drain) injection on the semiconductor substrate on two sides of the NMOS grid structure; forming side walls of the NMOS grid structure; and performing photo-etching and ion implantation of an NMOS source drain area on the semiconductor substrate on two sides of the side walls of the NMOS grid structure, wherein the order of the ion implantation is germanium (Ge), phosphorus (P), arsenic (As) and P. The method improves the performance of the NMOS.

Description

technical field [0001] The invention relates to the technical field of manufacturing semiconductor components, in particular to an N-type metal oxide semiconductor source-drain injection method. Background technique [0002] Semiconductor device fabrication refers to performing a series of complex chemical or physical operations on silicon wafers. Taking the manufacturing process of complementary metal oxide semiconductor (CMOS) as an example, such as figure 1 As shown, it mainly includes: [0003] Step 101: forming an N well, a P well, and a shallow trench isolation region (STI) on a semiconductor substrate of a silicon wafer. [0004] In the existing CMOS manufacturing process, the first step is to use a double well process to define the active regions of N-type metal oxide semiconductor (NMOS) and P-type metal oxide semiconductor (PMOS), so as to obtain N well and P well. Then, the STI is formed on the semiconductor substrate through processes such as photolithography ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L21/336H01L21/265
Inventor 刘金华
Owner SEMICON MFG INT (SHANGHAI) CORP