Method for manufacturing metal oxide semiconductor field effect transistor

Abstract

The invention discloses a method for manufacturing a metal oxide semiconductor field effect transistor, which comprises the following steps of: stacking a polysilicon grid structure on the upper surface of a silicon substrate of a wafer; constructing offset side walls on both sides of the polysilicon grid; performing light dope implantation in silicon substrate areas at the bottoms of the offset side walls on both sides of the polysilicon grid; performing primary quick heat treatment on the wafer; constructing side walls on outer sides of the offset side walls on the side wall of the polysilicon grid; performing large-dose ion implantation in the silicon substrate areas at the bottoms of the side walls distributed on both sides of the polysilicon grid to form a source electrode and a drain electrode respectively; performing secondary quick heat treatment on the wafer; and depositing a silicide barrier layer on the surface of the wafer, and etching the silicide barrier layer. By the scheme of the method, the performance of small-size metal oxide semiconductor field effect transistors can be improved.

Description

technical field [0001] The invention relates to the technical field of manufacturing semiconductor integrated circuits, in particular to a method for manufacturing metal oxide semiconductor field effect transistors. Background technique [0002] Metal oxide semiconductor (Metal Oxide Semiconductor, MOS) field effect transistors can be divided into two categories: N-channel silicon MOS field effect (NMOS) transistors and P-channel silicon MOS field effect (PMOS) transistors. There are two P+ regions on the substrate, which are called source and drain, and there is no conduction between the two poles. [0003] Such as figure 1 A schematic diagram of the structure of a PMOS transistor is shown. The silicon substrate 101 is implanted with VA group ions of lower concentration to form an N-type well 102 with lower doping concentration. Two lightly doped boron fluoride implanted regions 104 and 110, and two highly doped concentration regions 103 and 109 are formed on the N-type ...

AI Technical Summary

Problems solved by technology

It can be seen that when the gate width is small, the actual measured saturation current of the MOS tube is smaller than the target value, which is called the performance degradation problem of the small-sized MOS tube, so that the further improvement of the size of the MOS tube in performance Reduced limit

In other words, in order to maintain good performance of the MOS tube, the size of the MOS tube cannot be too small, and the reduction of the size of the semiconductor integrated circuit is the general trend of technological progress. Inconsistency between dimensions

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