[0023] Such as image 3 with Figure 8 , The controller of the present invention includes a voltage divider network H sence , Analog-to-digital converter, error voltage signal processing module, digital compensator, PWM signal output module, drive circuit and clock logic circuit. Switching power supply output data V out (t) After being divided by the voltage divider network, it is collected by ADC and quantified to obtain V o [n], and the preset discrete reference voltage V ref [n] The error voltage signal e[n] obtained by subtraction is sent to the digital compensator for data processing, and then modulated by the digital pulse width modulation circuit DPWM to generate the voltage control signal of the switching power supply, which is controlled by the drive circuit to increase the drive capacity Switching power supply power tube opening and closing. The controller adjusts the size of the duty cycle in each switching cycle of the switching power supply, that is, controlled by the synchronous clock signal syn(t) generated by the clock logic, and completes the ADC sampling and quantization, error generation, compensator output and accounting within one switching cycle Update of empty ratio control signal. The clock logic circuit is composed of a number of D flip-flops, AND gates, and NOT gates. The clock pulse generator circuit obtains the synchronized clock signal syn(t) by multiplexing the DPWM counter. When the rising edge of the clock signal syn(t) arrives, the ADC Start work, perform data sampling and quantization, update the output data of the error signal processing module and the digital compensator; when the falling edge of the clock signal arrives, trigger the DPWM duty cycle modulation module input to update the data, that is, the current duty cycle control signal d c [n] Read into DPWM for real-time processing. Among them, the synchronous clock signal syn(t) high level maintenance time is related to the working clock of the analog-to-digital converter ADC and the digital compensator, and is the sum of the ADC processing time and the digital compensator calculation time. When syn(t) maintains the high level, the front-end module is processing data, and the DPWM input signal has no data update. The DPWM input signal is updated after the falling edge of syn(t). In order to make the duty cycle output signal dpwm(t) of each cycle is the processing of the sampled value in the current switching cycle, so the DPWM output signal will be forced to be high during the high level of syn(t), syn (t) After the falling edge, use the actually generated duty cycle control signal to control the DPWM output dpwm(t) high level maintenance time, that is, the output dpwm(t) high level maintenance time consists of two parts: forced high power The flat time and accurate high-level time ensure that the PWM signal output by the DPWM in each switching period is to adjust the current system state of the switching period. In order to make the adjustment accurate, the high level time is forced to be as short as possible, that is, syn(t) is required to be a narrow pulse signal, and the high level maintenance time is short. Therefore, the ADC, error processing module and digital compensator are required to have high-speed processing speed . And in order to solve the problem of increased power consumption caused by the high-speed clock of ADC, error processing module and digital compensator, the synchronous clock syn(t) is used as the clock control signal. When the falling edge of syn(t) comes, it means that these three modules are processing End, cut off its working clock, and turn it on again when it needs processing next time to reduce system power consumption.
[0024] The following specifically describes the control method of the present invention.
[0025] In the digital power supply, the duty cycle is adjusted once every switching cycle, and the adjustment process is completed by the two modules of the digital compensator and DPWM. On the one hand, a digital compensator is required to calculate the current required duty cycle control signal d according to the magnitude of the error voltage e[n] quantized by the ADC and the working state of the system at the previous moment. c The size of [n]; on the other hand, DPWM is required to control the signal d according to this duty cycle c [n] Generate the duty cycle value dpwm(t) of the output PWM waveform in one switching period. Assuming that typical digital PID compensation is used, the relationship between the duty cycle control signal and the error voltage is
[0026] d c [n]=d c [n-1]+ae[n]-be[n-1]+ce[n-2] (1)
[0027] Among them, a, b, and c are the compensation coefficients of the PID, and the coefficient values can be determined according to the frequency stability design method of the switching power supply system, which is well known to those skilled in the art and will not be described in detail. Therefore, calculate the duty cycle control signal size d of the current switching cycle c [n] Need to use the duty cycle of the previous switching cycle d c [n-1], the error voltage e[n] of the current switching cycle, and the error voltages e[n-1], e[n-2] of the previous two switching cycles. Update once every switching cycle. A series D flip-flop can be used in the error signal processing module to save relevant data, and the synchronization clock syn(t) can be used to control each switching cycle to complete a data update. Because the D flip-flops in the error signal processing module and the duty cycle control signal processing module use the same synchronous clock signal, and there is a unidirectional data flow between the two, the data of the nth switching cycle is in this cycle It is updated by the error processing module and handed over to the digital compensator to calculate the duty cycle, but the calculated duty cycle d c [n] It must be the n+1th switching cycle to be updated by the D flip-flop in the duty cycle control signal processing module and control DPWM to adjust the duty cycle of the output signal dpwm(t). Adopting this kind of processing method can avoid the accumulation and loss of data, but it still causes a lag of the switching cycle. The output control signal of DPWM cannot control the current system state in time, which will inevitably bring adverse effects to the system.
[0028] In order to avoid the inability to perform real-time control of the power supply system due to the aforementioned data lag, it is desirable to complete the update of the error voltage signal and the duty cycle control signal at the same time within one switching cycle. Because the two are controlled by the same clock signal syn(t), the present invention proposes a processing method in which the error signal processing module is triggered on the rising edge of the clock to update the data, and the falling edge of the clock triggers the data update of the duty cycle control signal. However, due to the duty cycle control signal d during the period between the rising and falling edges of the synchronous clock signal c [n] has not been updated yet, and its value is still the result of the calculation of the error voltage e[n] of the last switching cycle and other state-related data in the circuit through the digital compensator. Considering that the duty cycle in the actual switching power supply system is usually not very small, that is, the PWM signal will not change to a low level in a short period of time after a switching cycle starts. Based on this feature, the synchronous clock syn(t) is set as a narrow pulse signal with a small duty cycle, and the PWM output signal is forced to be high during the time period between the rising edge and the falling edge of the pulse. After the falling edge of the synchronous clock signal, use the duty cycle control signal d generated by the switching period c [n] Controls the duty cycle of the PWM signal dpwm(t), so that it can be ensured that the PWM signal output in each switching period is the system error voltage signal of the switching period. The size of the narrow pulse signal is related to the working clock of the analog-to-digital converter ADC and the digital compensator. It is the sum of the processing time of the ADC and the calculation time of the digital compensator. Within the pulse time of a clock signal, syn(t ) Signal as the selection signal, using DPWM actual output and power supply voltage V DD As the selected signal of the one-of-two selector, when the syn(t) signal is high, the DPWM output is connected to the power supply voltage, that is, the DPWM output signal is forced to be high.
[0029] The circuit structure, working principle and working process of the present invention will be further described below with reference to the drawings and examples.
[0030] See figure 2 with image 3 In the optimized digital control switching power supply cross-clock domain controller of the present invention, the digital compensator is included in the duty cycle control signal processing module, and the syn(t) signal generated by the system synchronization clock generation circuit is added to the DPWM module to replace the original external signal. Of the clock signal. The rising edge of the synchronous clock syn(t) means the beginning of a switching cycle, and this rising edge will trigger the data update in the D flip-flop in the error voltage signal processing module in the figure. It is high after the rising edge of the synchronous clock. During the high level, the duty cycle control signal has not been updated yet, and its value is still the data of the previous switching cycle, but in this case, the synchronous clock controls the multiplexer to force The output of DPWM is at a high level, and the duty ratio control signal of the previous switching period is not allowed to control the duty ratio of the current switching period PWM signal. During this period, the digital compensator completes digital compensation according to the compensation algorithm shown in formula (1). The falling edge of the synchronous clock signal triggers the duty cycle control signal of the current switching cycle to be updated through the D flip-flop, and the updated data is passed to DPWM to control the duty cycle of the PWM signal, and the synchronous clock signal jumps to low level. At this time, the multiplexer outputs the actual duty cycle signal of the current DPWM switching cycle. The data changes with the synchronous clock signal as follows Figure 4.
[0031] The relationship between the output value of DPWM dpwm(t) and the synchronous clock syn(t) can be seen in the time period when the synchronous clock signal syn(t) is high, the PWM output is forced to be high, and when syn(t) becomes low , PWM outputs the actual duty cycle value. Therefore, in this circuit structure, the size of the minimum duty cycle signal that the system can output is limited by the clock synchronization signal, and the ideal zero duty cycle cannot be achieved. However, judging from the actual working situation of the switching power supply, the system basically does not require the duty cycle signal to be zero in one switching cycle in the PWM working mode, so the limitation of the minimum duty cycle signal that can be output has no effect on the actual circuit work. influences. The synchronous clock signal and duty cycle signal of the controller of the present invention are as Figure 7 , Where 1 is a duty cycle signal, and 2 is a synchronous clock signal.
[0032] The synchronous clock generating circuit in the present invention is realized by designing the pulse generating circuit of the counter in the DPWM part of the multiplexed digital power supply, see Figure 5 , The clock logic circuit is composed of a number of D flip-flops, AND gates, and NOT gates. The clock pulse generating circuit is obtained by multiplexing the counter of DPWM. The output signal of the counter is fed back to the counter input after the first D flip-flop is delayed. At the same time, the counter The output signal is inverted and sent to the second D flip-flop, the inverted end signal of the second D flip-flop is connected to the input end of the third D flip-flop, and the non-inverting output ends of the second D flip-flop and the third D flip-flop are sent to Enter a two-input AND gate, and the output of the two-input AND gate is the synchronous clock signal. In this circuit, the rising edge of the input clock signal clk_in triggers the first D flip-flop DFF to update data, causing the counter output signal N[n-1:0] to increase by one. After counting starts (2 n -1) In a counting period, the highest bit N[n-1] of the counter output is always ‘0’; after 2 n After a period, the counter is full, N[n-1] is '1', and the synchronous clock signal syn(t) remains low during this period of time. (2 n +1) N[n-1] changes from '1' to '0' again after a period. At this time, the Q terminal of the second D flip-flop DFF0 outputs a high level, and the NQ terminal outputs a low level; while the output of the third D flip-flop DFF1 still maintains the previous '1', and the outputs of the two D flip-flops pass the AND logic Afterwards, the synchronization signal is changed to a high level. After a period of the clk_in signal, the output of the third D flip-flop DFF1 changes to a low level, and the synchronization signal also changes to a low level. When the counter output value becomes zero again, the synchronization signal will undergo a positive transition again, so the period of the synchronization signal is exactly the switching period, and the duty ratio is 1/32. The working waveforms of the counter and synchronous clock generator circuit of the digital control switching power supply across the clock domain controller are as follows: Image 6 Shown. In addition, since the positive transition of the synchronization signal occurs at the moment when the counter outputs the zero value, the PWM signal will also undergo a positive transition. Therefore, the positive transition of the synchronization signal means the beginning of a switching cycle, and the synchronization signal can fully meet the system data synchronization Needs.
