Method for manufacturing 6-inch POWERMOS transistor epitaxial layer

A manufacturing method and epitaxial layer technology, which are applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of reducing the effective thickness of the epitaxial layer, decreasing the yield of the device, and poor uniformity, so as to suppress the self-doping phenomenon. , Consistency improvement, the effect of improving electrical performance and yield
CN102157359AActive Publication Date: 2011-08-17FUJIAN FUSHUN MICROELECTRONICS
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Patent Information

Authority / Receiving Office
CN Β· China
Patent Type
Applications(China)
Current Assignee / Owner
FUJIAN FUSHUN MICROELECTRONICS
Publication Date
2011-08-17

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Abstract

The invention relates to a method for manufacturing a 6-inch power metal oxide semiconductor (POWERMOS) transistor epitaxial layer. The method is characterized by comprising the following steps of: 1) selecting a suitable POWERMOS transistor substrate slice and performing a certain preprocessing; 2) performing HCl gas-phase corrosion on the substrate slice at a certain temperature; 3) performing primary H2 speed-variable sweeping; 4) depositing an undoped intrinsic layer with the thickness of 1 to 2 mu m on the substrate slice; 5) performing secondary H2 speed-variable sweeping; and 6) forming a second epitaxial layer on the intrinsic layer. By the method, an autodoping phenomenon is inhibited to the maximum at a high temperature and substrate impurities are effectively prevented from diffusing and doping to the epitaxial layer, so that the resistivity uniformity and the width of a transition area are ensured; therefore, the requirements on both the breakdown voltage (BVDSS) and the on-resistance (RDSON) of the device are met.
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Description

Technical field

[0001] The invention relates to a method for manufacturing an epitaxial layer of a 6-inch POWERMOS tube. Background technique

[0002] With the development of electronic devices, devices that can control large currents and high voltages are being widely put into practical applications. POWERMOS is a kind of device produced from this, and it is very popular because of its precise control. However, 6-inch POWERMOS epitaxy is relatively thick and high resistivity, and its surface area is relatively large, which is 4 inches. 2.25 times, 1.44 times that of 5 inches, so there are special requirements and standards for epitaxial wafers.

[0003] The structure of POWERMOS epitaxial wafers is to grow a layer of high resistivity epitaxial layer (N+ / N) on an N+ substrate. The ordinary epitaxial process cannot be achieved. If the "mass-transfer" process is used, the base The silicon on the seat will be unevenly transferred to the back of the silicon wafer, and the flatness ca...

Claims

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