Manufacturing method of silicon epitaxial wafer for low voltage tvs

Abstract

The invention relates to a manufacturing method for a silicon epitaxial wafer, in particular to a manufacturing method for a silicon epitaxial wafer of a low-voltage TVS (transient voltage suppressor). In the technical scheme, when a P-shaped epitaxial layer is grown on an N-shaped substrate, HCl (Hydrogen Chloride) is adopted for gas corrosion of impurities and metal atoms on the surface of the substrate, high-temperature large-volume hydrogen is then adopts for blowing, hydrogen is adopted for high-temperature baking of impurity atoms on the N-shaped substrate, and finally a pre-pass P-typedopant (B2H6) is grown on the epitaxial layer. Therefore, the concentration of gas-phase impurities in an epitaxial reactor and the concentration of impurities absorbed to a base and the surface of the substrate can be reduced, the degree of compensation of N-type impurities and P-type impurities can be decreased, and a clean growth zone can be formed. Moreover, gas-phase conditions in the reactor can be improved, the stability of the thickness of the epitaxial layer can be guaranteed, and thus, the stability of protective voltage for devices can be ensured.

Description

technical field [0001] The invention relates to a silicon epitaxial wafer, in particular to a method for manufacturing a silicon epitaxial wafer for a low-voltage TVS, and belongs to the field of silicon epitaxial wafer manufacturing. Background technique [0002] With the continuous development of electronic communication technology, communication equipment with high density, miniaturization and complex functions has become the mainstream of the market. However, due to its low operating voltage, it is extremely vulnerable to the threat of electrostatic discharge (ESD), and even has destructive consequences. At the same time, due to the gradual shrinking of the feature size of devices, the feature size of IC products has reached the order of tens of nanometers, and the active layer and gate oxide layer of integrated circuits are relatively thinner, so they are more sensitive to instantaneous current and voltage shocks in the circuit. Therefore, ESD damage has become one of ...

AI Technical Summary

Problems solved by technology

Therefore, ESD damage has become one of the main reliability problems of integrated circuits. Studies have shown that in most cases ESD damage is manifested as potential damage, so that the long-term reliability of the device is seriously affected. Therefore, the circuit must have a low clamping voltage. Protection devices with fast response time to ensure effective ESD protection

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