Memory controller and method for controlling commands

Abstract

The invention discloses a memory controller and a method for controlling commands. When an inactivated RANK in external DRAM is required to be accessed, an ACT command and an access command with low rate are generated in parallel by aiming at the BANK, and the parallel ACT command and the access command with low rate are carried out serial output according to high speed successively to an external DRAM bus, thereby, high performance can be ensured when interleaved access of the BANK is carried out. And the problems of high internal work frequency of memory controller, power supply and heat radiation are simultaneously avoided.

Description

technical field [0001] The present invention relates to memory controller (Memory Controller) technology, particularly relate to mainly applicable to the 2nd generation double data rate (Double Data Rate2, DDR2) Synchronous Dynamic Random Access Memory (Synchronous Dynamic Random Access Memory, SDRAM) and the 3rd generation A memory controller of a double data rate (Double Data Rate 3, DDR3) SDRAM, and a command control method that can be used to realize the memory controller. Background technique [0002] In today's computer systems, such as figure 1 As shown, the CPU and I / O devices need to access the data in the external memory system through the memory controller. The external memory system connected to the memory controller is realized by the DRAM device. Currently, DDR2 SDRAM and DDR3 SDRAM are the most widely used. Therefore, the external memory system may also be referred to as an external DRAM system. [0003] The memory controller is mainly responsible for readin...

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Problems solved by technology

[0024] Although as Figure 7 The shown single-rate memory controller can achieve high-performance Bank interleaving access with 100% bus efficiency, but the operating frequency of the Ctrl module in the single-rate memory controller must be the same as that of the external DDR2 SDRAM bus. When the external DDR2 SDRAM bus When working at a higher frequency, the Ctrl module must also work at a higher frequency, and because the logic function of the Ctrl module is very complex, it is difficult to meet the setup time and hold time between logic registers when it works at a high frequency

For example, if the current most high-end Xilinx or Altera FPGA device is used to implement the Ctrl module, its IO interface can meet the frequency above 1GMHz, but its internal logic can only generally run below 300MHz, which obviously cannot meet the current popular 333MHz DDR2 SDRAM and 400MHz DDR2 SDRAM Operational Requirements

In addition, when the functionally complex Ctrl module works at a very high frequency, the power consumption of the entire memory controller will be very large, which will cause power supply and heat dissipation problems

[0025] It can be seen that the BANK interleaving access performance of DDR2 SDRAM cannot be guaranteed at a lower frequency in the prior art

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