Formation method of metal gate and MOS transistor

Abstract

The invention relates to a formation method of a metal gate and an MOS transistor. The method comprises the following steps that: a semiconductor substrate is provided as well as a sacrificial oxide layer and a polysilicon grid are successively formed on the semiconductor substrate, wherein spacers are arranged at positions that are at two sides of the polysilicon grid and are on the semiconductor substrate; interlay dielectric layers are formed on the semiconductor substrate as well as the surfaces of the interlay dielectric layers are flush with tops of the polysilicon grid and the spacers; the polysilicon grid is removed until the sacrificial oxide layer is exposed so as to form a groove; silicon nitride layers in the spacers are removed by a predetermined thickness, wherein the predetermined thickness is consistent with the thickness of the sacrificial oxide layer; the sacrificial oxide layer in the groove is removed as well as surfaces of the interlay dielectric layers and oxygen ambient silica layers in the spacers are flush with the tops of the silicon nitride layers; and the groove is filled with a metal layer so as to form a metal gate. According to the formation method provided in the invention, an occurrence of a problem that a metal circuit is caused by metal residue during a grinding process of a metal layer can be prevented; and stability and reliability of a semiconductor device can be improved.

Description

Technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a method for forming a metal gate and a MOS transistor. Background technique [0002] In the manufacture of semiconductor devices, leakage has always been an important factor in reducing processor yield, hindering performance improvement and reducing power consumption. As the feature size of semiconductor devices becomes smaller and smaller, the area occupied by the corresponding core devices is correspondingly reduced, resulting in a substantial increase in energy density per unit area, more prominent leakage problems, and increased power consumption. Therefore, in the process below 45 nanometers, the traditional silicon dioxide gate dielectric layer process has encountered a bottleneck and cannot meet the process requirements of semiconductor devices; to solve the above bottleneck, high dielectric constant (high k: k The value is greater than or equal to 10) The dielectric m...

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Problems solved by technology

[0008] like Figure 5 As shown, when the conventional high-k metal gate is formed, there will be a metal layer remaining on the surface of the silicon oxide layer 11 in the interlayer dielectric layer 2 and the sidewall 1, which will cause a short circuit phenomenon in the subsequently formed semiconductor device and reduce the reliability of the semiconductor device. Electrical properties of the device

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