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Super junction device with multiple embedded P islands and N channels and preparation method thereof

A superjunction device and channel technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problem of uneven electric field distribution in the drift region, and achieve the effect of solving uneven electric field distribution

Active Publication Date: 2012-07-18
上海功成半导体科技有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide an embedded multi-P island N-channel superjunction device and its preparation method, which are used to solve the problem of uneven electric field distribution in the drift region in the prior art

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  • Super junction device with multiple embedded P islands and N channels and preparation method thereof
  • Super junction device with multiple embedded P islands and N channels and preparation method thereof
  • Super junction device with multiple embedded P islands and N channels and preparation method thereof

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Embodiment 1

[0045] The invention provides a method for preparing an N-channel superjunction device with embedded multi-P islands. The method includes the following steps:

[0046] In step 1), a semiconductor substrate 21 is provided, and a layer of N-type drift region 22 is prepared on the semiconductor substrate 21 by N-type ion implantation; specifically, the semiconductor substrate 21 is a bulk silicon substrate or SOI substrate. see figure 2 , as shown in the figure, in this embodiment, the semiconductor substrate 21 is an SOI substrate as an example for illustration, and the N-type drift region 22 is formed in the top silicon layer of the SOI substrate, specifically, in N-type ions of group V elements (such as phosphorus, arsenic, antimony, etc.) are doped into the top silicon of the SOI substrate to replace the positions of silicon atoms in the crystal lattice to form an N-type drift region 22 .

[0047] Then, provide a mask plate 3 with multiple groups of ion implantation window...

Embodiment 2

[0052] This embodiment is the same as step 1) and step 4) in the above-mentioned embodiment 1, so it will not be described in detail. In step 2 in this embodiment, boron ions are implanted into the N-type drift region 22 repeatedly and borrowed The concentration distribution of boron ions is controlled by the shielding of the mask plate 3, and annealed in step 3), and then a plurality of mutually spaced and horizontally parallel and longitudinally parallel arrangements can be formed in the N-type drift region 22. The island-shaped P region 23, as shown in Figure 7 shown.

Embodiment 3

[0054] The present invention also provides an embedded multi-P-island N-channel superjunction device, please refer to Figure 6 , which is a schematic diagram showing the structure of an embedded multi-P island N-channel superjunction device according to the present invention. As shown in the figure, the embedded multi-P-island N-channel superjunction device includes: a semiconductor substrate 21 formed on the semiconductor substrate The N-type drift region 22 on the bottom 21, the P-type body region 24 on one side of the N-type drift region 22, and the N-type drain region 28 on the other side of the N-type drift region 22, the P The body 24 includes an N-type source region 25 , a P-type body contact region 27 and a gate oxide layer 27 .

[0055] A plurality of island-shaped P regions 23 are formed in the N-type drift region 22 , and each of the island-shaped P regions 23 linearly decreases from the N-type source region 25 to the N-type drain region 28 . The semiconductor sub...

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Abstract

The invention provides a super junction device with multiple embedded P islands and N channels and a preparation method thereof. The super junction device comprises a semiconductor substrate, an N-type drift region formed on the semiconductor substrate, P-type body regions on one side of the N-type drift region, and N-type leakage regions on the other side of the N-type drift region, wherein a plurality of parallel island-shaped P areas are formed in the N-type drift region at intervals, and each island-shaped P area is gradually diminished in a linear manner from N-type source regions to the N-type leakage regions; the function of the substrate-assisted depletion effect is sequentially enhanced from source ends to leakage ends under a high voltage, so that the island-shaped P areas are correspondingly decreased from the source ends to the leakage ends, and accordingly, the complementation and offset to the substrate-assisted depletion effect are realized, and the purpose of charge balance is achieved.

Description

technical field [0001] The invention relates to a semiconductor device and a preparation method thereof, in particular to an embedded multi-P island N-channel superjunction device and a preparation method thereof. Background technique [0002] Power integrated circuits are sometimes called high-voltage integrated circuits, which are an important branch of modern electronics. They can provide new circuits with high speed, high integration, low power consumption and radiation resistance for various power conversion and energy processing devices, and are widely used in electric power Daily consumption fields such as control systems, automotive electronics, display device drivers, communications and lighting, as well as many important fields such as national defense and aerospace. The rapid expansion of its application scope has also put forward higher requirements for the high-voltage devices in its core part. [0003] For the power device MOSFET, under the premise of ensuring...

Claims

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Application Information

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IPC IPC(8): H01L21/336H01L29/78H01L29/06
Inventor 程新红王中健徐大伟夏超曹铎贾婷婷宋朝瑞俞跃辉
Owner 上海功成半导体科技有限公司
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