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Floating gate type EEPROM (Electrically Erasable Programmable Read Only Memory) device and manufacturing method thereof

A manufacturing method and floating gate technology, which is applied in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., can solve the problems of reducing size and performance, increase voltage coupling efficiency, maintain device area, and reduce device area Effect

Inactive Publication Date: 2012-10-31
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Abstract
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Problems solved by technology

This makes the existing floating gate EEPROM face the contradiction between size reduction and performance improvement.

Method used

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  • Floating gate type EEPROM (Electrically Erasable Programmable Read Only Memory) device and manufacturing method thereof
  • Floating gate type EEPROM (Electrically Erasable Programmable Read Only Memory) device and manufacturing method thereof
  • Floating gate type EEPROM (Electrically Erasable Programmable Read Only Memory) device and manufacturing method thereof

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Embodiment Construction

[0025] see figure 2 , which is a specific embodiment of the floating gate EEPROM device of the present invention. Wherein, each memory cell includes a storage transistor 1a and a selection transistor 1b, both transistors are fabricated on the substrate 10 and the gate oxide layer 11, and share a heavily doped source and drain region 10a. The storage transistor 1a is a floating gate transistor, including two gates, a polysilicon floating gate 12 located below and a polysilicon control gate 14 located above, and a dielectric layer 13 separates the two gates 12 and 14 . A small portion of the gate oxide layer 11 is thinner in the area of ​​the storage transistor 1a, which is called the tunnel oxide layer 11a.

[0026] Such as figure 1 As shown, in the existing floating gate type EEPROM device, the upper and lower surfaces of the dielectric layer 13 are flat planar shapes. The floating gate 12 is in contact with the lower surface of the dielectric layer 13, and the contact sur...

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Abstract

The invention discloses a floating gate type EEPROM (Electrically Erasable Programmable Read Only Memory) device. A memory cell of the EEPROM device comprises a memory transistor and a selection transistor, wherein the memory transistor comprises a floating gate positioned at the lower part and a control gate positioned at the upper part; and a dielectric layer is arranged between the floating gate and the control gate, and is in a curved surface shape. The invention further discloses a manufacturing method of the device, which mainly comprises the step that the floating gate is subjected to shallow trench etching, so that the dielectric layer is in the concave curved surface shape. Compared with the traditional flat dielectric layer, the capacitance area is increased; and the increased capacitance is proportional to the depth of a shallow trench, so that the voltage coupling efficiency and the coupled voltage are increased, and the area of the existing device can be kept or even reduced.

Description

technical field [0001] The present invention relates to an NVM (non-volatile memory, non-volatile memory) device, in particular to an EEPROM (Electrically Erasable Programmable Read Only Memory, electrically erasable programmable read-only memory) device. Background technique [0002] In order to obtain higher performance and larger storage capacity, embedded NVM hopes that the area of ​​the storage unit should be as small as possible. Embedded NVM technology has been developed so far, mainly including floating gate (floating gate), split gate (split gate) and SONOS (Silicon-Oxide-Nitride-Oxide-Silicon, silicon oxide nitride oxide silicon) three technologies. Floating-gate NVM has the advantage of higher data retention than other technologies, but faces difficulties in size reduction. This is because the reduction in the size of the floating gate itself will result in a reduction in the dielectric area between the floating gate and the control gate, that is, a reduction in ...

Claims

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Application Information

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IPC IPC(8): H01L27/115H01L29/788H01L29/423H01L21/8247
Inventor 陈广龙陈昊瑜
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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