Method for forming non-load-effect large size groove

Abstract

The invention relates to the field of semiconductor manufacture, in particular to a method for forming a non-load-effect large size groove. Large size and small size contact hole grooves are filled in a deposition medium layer after the metal hard mask etching process, the grinding process is utilized to form a dish recessed area on the large size grooves, load effect formed in etching of the grooves with large size difference is removed, and connection efficacy lose caused by residue caused by the load effect in the large size grooves is effectively avoided. The method improves product yield, further expands an etching process window and further improves etching process performance.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a large-size trench without load effect. Background technique [0002] Metal hard mask single damascene trench etching process is a key step in the copper wire interconnection process in the back section of the chip. After the etched trench is filled and polished with copper, the first layer of copper wire is formed, and the contact with the lower layer The contacts are connected, and the etching body is generally low dielectric constant silicon oxide or F-containing silicon oxide (FSG) film. [0003] Figure 1-5 It is a schematic diagram of the process flow structure of metal hard mask single damascene trench etching in the background technology of the present invention; as Figure 1-5 As shown, in the single damascene trench etching process of silicon oxide film containing F, silicon nitride (SiN) layer 12, FSG Layer 13, metal hard mask layer (Ti...

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Problems solved by technology

[0004] However, the single damascene trench etching process will produce a loading effect, which is mainly reflected in two aspects: first, when etching a silicon oxide trench, a large The concentration of etchant in the small-sized etching area (such as groove 17) is lower than that of the small-sized etching area (such as groove 16), the etching rate is slow, and the larger the difference in size, the more prominent the difference; Second, when etching silicon oxide trenches, due to the use of low fluorine-to-carbon ratio gases that generate more polymers to ensure the etching sidewall morphology, such as C4F8, C4F6 and other gases will cause more intense etching reactions in large-sized etching areas, resulting in more polymers and lower etching rates. Slow, coupled with ion reflection at the edge of the large-scale etched area, resulting in the formation of a large-scale etched area with a high middle and low etching profile on both sides

Under the combined effect of these two effects, the small-sized trench has the fastest etching rate, the large-sized trench has the second largest etching rate on both sides, and the middle etching rate is the slowest. The greater the size difference, the greater the etching rate difference. more obvious and difficult to overcome

In order to ensure that the ILD loss of small-sized trenches is not too large, it is necessary to control the over-etching time. In order to ensure that the middle silicon nitride of large-sized trenches can be etched clean, the over-etching time must be sufficient. If the etch rate of the trenches differs too much, the debugging window of this process will be very small. In extreme cases, silicon nitride residues in the middle of large-sized trenches will result, which will cause connection failure.

[0005] such as As shown in Figure 3 , after the main etching process, the bottom of the formed small-sized via hole 161 has been partially etched into the remaining silicon nitride (SiN) layer 121, while the large-sized via hole 171 The bottom is also located in the residual FSG layer 131, and forms a raised residual FSG 18 in the middle; such as Figure 4, after continuing the over-etching process, although the bottom of the formed large-size through hole 172 is partially etched to the remaining silicon nitride (SiN) layer 122, there are still residual FSG 181, at this time, the bottom of the formed small-sized via hole 162 has been etched into the relatively deep remaining silicon nitride (SiN) layer 122; for example, Figure 5, after the etching process of the etching barrier layer is performed finally, the formed small-sized via hole 163 is located in the remaining interlayer Dielectric layer 111, and silicon nitride 19 remains at the bottom of the large-sized through hole 173, which causes connection failure and reduces product yield

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