The invention discloses a multilayer line manufacturing process of wafer-level micro electromechanical system chip encapsulation technology. The process comprises the following flows of: pre-processing, wafer thinning, exposure and development, etching, insulating layer coating, laser drilling, copper sputtering, chemical copper plating pretreatment, chemical copper plating, electric copper plating, exposure and development, copper etching, insulating layer coating and exposure and development, laser drilling, copper sputtering, chemical copper plating pretreatment, chemical copper plating, electric copper plating, exposure and development, copper etching, N (N is more than or equal to 0) times (insulating layer coating and exposure and development, laser drilling, copper sputtering, chemical copper plating pretreatment, chemical copper plating, electric copper plating, exposure and development, copper etching), acid chemical nickel plating, chemical cyanide gilding, solder mask coating and exposure and development, BGA forming, and subsequent cutting, testing and packing. The process for forming a multilayer mutual conduction line effectively deals with product size reduction and line denseness, and improves the yield of products.