Multilayer line manufacturing process of wafer-level micro electromechanical system chip encapsulation technology

A technology of micro-electromechanical systems and chip packaging, which is applied in the process of producing decorative surface effects, micro-structure technology, metal material coating process, etc. Wait for the problem to achieve the effect of improving product yield

Inactive Publication Date: 2010-10-27
HUATIAN TECH KUNSHAN ELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Generally, the line width and the line or pad spacing are in the range of 40-100 microns, and the spacing between the edges of the pads is mostly about 300 microns, and three to four lines are electrically interconnected from the inside and outside of the wafer within the spacing of about 300 microns. And it meets the requirements of line width and line spacing. Under the current technical conditions, the operation faces many problems, such as t

Method used

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Examples

Experimental program
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Example Embodiment

[0033] Embodiment: A multilayer circuit manufacturing process of wafer-level MEMS chip packaging technology, using the IC surface of the wafer as the front surface of the wafer, and proceeding according to the following process steps:

[0034] ①. Pre-process: forming a polymer resin photoresist surface that matches the IC on the front of the wafer on one side of the glass, and bond the photoresist surface of the glass with the front surface of the wafer by a bonding machine;

[0035] ②. Wafer thinning: grinding and thinning the wafer from the back to the set size and thickness, and then plasma etching the back of the wafer to remove the internal stress generated during grinding;

[0036] ③ Exposure and development: apply photoresist on the back of the wafer and bake it, expose the photoresist on the back of the wafer and develop it according to the design, and develop the photoresist applied to the area on the back of the wafer that needs to be etched;

[0037] ④. Etching: Put the wafe...

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PUM

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Abstract

The invention discloses a multilayer line manufacturing process of wafer-level micro electromechanical system chip encapsulation technology. The process comprises the following flows of: pre-processing, wafer thinning, exposure and development, etching, insulating layer coating, laser drilling, copper sputtering, chemical copper plating pretreatment, chemical copper plating, electric copper plating, exposure and development, copper etching, insulating layer coating and exposure and development, laser drilling, copper sputtering, chemical copper plating pretreatment, chemical copper plating, electric copper plating, exposure and development, copper etching, N (N is more than or equal to 0) times (insulating layer coating and exposure and development, laser drilling, copper sputtering, chemical copper plating pretreatment, chemical copper plating, electric copper plating, exposure and development, copper etching), acid chemical nickel plating, chemical cyanide gilding, solder mask coating and exposure and development, BGA forming, and subsequent cutting, testing and packing. The process for forming a multilayer mutual conduction line effectively deals with product size reduction and line denseness, and improves the yield of products.

Description

technical field [0001] The invention relates to the field of manufacturing technology of circuits and welding pads in wafer-level MEMS chip through-silicon hole packaging technology products. Background technique [0002] At present, in the manufacturing process of wafer-level micro-electromechanical system (English abbreviation: MEMS) chip through-silicon via (English abbreviation: TSV) packaging technology, single-layer wiring is generally used, and the conductive block inside the wafer is exposed through the previous process (English abbreviation: TSV). Abbreviation: pad), aluminum sputtering, photoresist coating exposure development, nickel plating, photoresist removal, aluminum removal of photoresist layer, etching, nickel gold plating, solder mask coating exposure development, solder paste printing , reflow soldering and other processes to electrically interconnect the inside and outside of the wafer, and produce the required lines and ball grid array (English abbrevia...

Claims

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Application Information

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IPC IPC(8): B81C1/00
Inventor 陈闯
Owner HUATIAN TECH KUNSHAN ELECTRONICS
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