Optimizing design method of nanometer technical metal layer map

Abstract

The embodiment of the invention provides an optimizing design method of a nanometer technical metal layer map. The method comprises the steps as follows: physically designing a standard unit metal layer map, and then adjusting the arrangement and direction of metal lines of the metal layer map; optimizing the width and spacing of the metal lines at the input end of the metal layer map; optimizing the width and spacing of the metal lines at the output end of the metal layer map; and optimizing the width and spacing of the metal lines at the boundary of the metal layer map, so as to meet the preset width and the preset spacing of the metal lines. With the adoption of the optimizing method provided by the embodiment of the invention, the turning in the metal layer map is reduced, and the metal layer map can be uniform in density distribution; the optics proximity correction and modification area required by the metal layer map can be optimized, the data volume in the optics proximity correction and modification and the modification time can be reduced, the manufacturability of a chip is improved, and the manufacturing cost of the chip is saved.

Description

technical field [0001] The invention relates to the technical field of integrated circuit manufacturing, in particular to an optimal design method of a metal layer layout of a nanometer process. Background technique [0002] At the technology node below 90nm, the feature size of the chip is already close to or even smaller than the wavelength of the light wave used in the photolithography process. Therefore, in the lithography process, due to the interference and diffraction effects of light waves, there are certain deformations and deviations between the lithography pattern and the layout pattern on the actual wafer. This error in lithography directly affects the manufacturability of the chip. (Design For Manufacturing, DFM). In order to obtain high-resolution and more realistic layout graphics, optical proximity correction (Optical Proximity Correction, OPC) and other photolithography technologies are applied to the mask manufacturing process. A pattern as close as possi...

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Problems solved by technology

[0005] In view of this, the present invention aims to provide a method for optimizing the design of the metal layer layout of the standard cell library of nanotechnology, so as to solve the problem of certain deformation and deviation between the lithography pattern and the layout pattern on the actual wafer in the prior art problems, reduce the amount of OPC correction data and correction time, improve the manufacturability (DFM) of the chip, and save the manufacturing cost of the chip

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