N-channel metal oxide semiconductor (NMOS) transistor and forming method thereof

Abstract

The invention relates to an N-channel metal oxide semiconductor (NMOS) transistor and a forming method thereof. The NMOS transistor comprises a semiconductor substrate, a gate structure and source / drain regions, wherein the gate structure is positioned on the surface of the semiconductor substrate; the source / drain regions are positioned in the semiconductor substrate on the two sides of the gate structure and comprise first silicon carbide stress layers positioned in the semiconductor substrate on the two sides of the gate structure, and second silicon carbide stress layers which are positioned at the bottoms of the first silicon carbide stress layers and in contact with the first silicon carbide stress layers; and the first silicon carbide stress layers protrude out of one side of the gate structure. The first silicon carbide stress layers protrude out of one side of the gate structure, and the depth of the second silicon carbide stress layers is large, so that tensile stress generated by the source / drain regions of the NMOS transistor is high, the lattice spacing of a channel region of the NMOS transistor is large, and electron mobility is high.

Description

technical field [0001] The invention relates to semiconductor manufacturing technology, and more specifically, the invention relates to an NMOS transistor capable of improving carrier mobility and a forming method thereof. Background technique [0002] It is well known that stress can change the energy gap and carrier mobility of silicon materials. With the in-depth research on the piezoresistance effect of silicon materials, the industry has gradually realized that stress can be used to increase the carrier mobility of MOS devices, that is, strained silicon technology (Strained Silicon). [0003] The U.S. patent document with publication number US2007 / 0196992A1 discloses a strained silicon CMOS transistor with silicon germanium and silicon carbide source / drain regions, please refer to figure 1 , including: a semiconductor substrate 10, the semiconductor substrate 10 includes a region A where an NMOS transistor is to be formed and a region B where a PMOS transistor is to be...

AI Technical Summary

Problems solved by technology

[0005] However, in the prior art, the source / drain region of the transistor is a rectangular structure, the stress on the channel region under the gate structure is limited, the improvement of the carrier mobility is small, and the performance of the transistor is limited. Therefore, the industry needs MOS devices capable of greater stress

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