Method for manufacturing high-density QFN (quad flat no-lead) package device

Abstract

The invention discloses a method for manufacturing a high-density QFN (quad flat no-lead) package device. The chip load and pins of the manufactured high-density QFN package device do not need to be based on a lead frame manufactured in advance, chip carriers and pins with step structures are formed by organically combining etching, electroplating and chemical plating methods in a package technical process, insulated filling materials are arranged in grooves among outer chip carriers and outer pins and among the outer pins by an injection molding or silk-screen printing method, plastic package materials are used for coating and sealing, and the independent chip carriers and the independent pins are formed by an etching or mechanical grinding method. The manufactured QFN package device with the arranged multi-turn pins has high I / O (input / output) density and fine reliability.

Description

technical field [0001] The invention relates to the technical field of manufacturing high-density QFN components, in particular to a method for manufacturing quadrilateral flat no-lead packages with high I / O density. Background technique [0002] With the development of electronic products such as mobile phones and notebook computers towards miniaturization, portability, ultra-thinness, multimedia and low-cost requirements for popularization, high-density, high-performance, high-reliability and low-cost packaging forms and Its assembly technology has been developed rapidly. Compared with expensive BGA and other packaging forms, the new packaging technology developed rapidly in recent years, that is, Quad Flat Non-lead Package (QFN) package, has good thermal and electrical properties, small size, Many advantages such as low cost and high productivity have triggered a new revolution in the field of microelectronic packaging technology. [0003] Figure 1A and Figure 1B Res...

AI Technical Summary

Problems solved by technology

[0004] With the improvement of IC integration and the continuous enhancement of functions, the number of I / Os of ICs increases, and the number of I / O pins of corresponding electronic packages also increases accordingly. The pins of the ring are arranged around the chip carrier, which limits the increase in the number of I / Os and cannot meet the needs of high-density ICs with more I / Os.

Even if the traditional QFN package with non-step structure design has multi-turn pins, it cannot effectively lock the plastic packaging material, resulting in low bonding strength between the lead frame and the plastic packaging material, which is easy to cause delamination between the lead frame and the plastic packaging material and even leads Or the chip carrier falls off, and it cannot effectively prevent moisture from diffusing into the electronic package along the interface between the lead frame and the plastic packaging material, which seriously affects the reliability of the package.

Even if the traditional QFN package has a stepped structure design, it can only be realized based on single-turn pins or staggered multi-turn pins, and each outer end of all pins must extend to one side of the package body and be exposed to the external environment , causing moisture to easily diffuse into the package, affecting the reliability of the product, and due to space constraints, it is impossible to achieve higher density packaging

The chip load and pins of the traditional QFN package must be based on the pre-fabricated lead frame structure, otherwise the chip load and pins cannot complete all the packaging process due to lack of mechanical support and connection

Traditional QFN packages need to paste tape on the back of the lead frame in advance to prevent overflow during the plastic sealing process.

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