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Manufacturing method of semiconductor element

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of difficult integration of manufacturing processes and complex manufacturing process steps.

Active Publication Date: 2017-07-28
UNITED MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] However, both methods have their own disadvantages
For example, it will make the manufacturing process steps more complicated, or cause difficulties in integrating with the current manufacturing process

Method used

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  • Manufacturing method of semiconductor element
  • Manufacturing method of semiconductor element
  • Manufacturing method of semiconductor element

Examples

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no. 1 example

[0063] The temporary material layer can be a sacrificial spacer in the selective epitaxial growth process. The selective epitaxial growth process can introduce stress into the gate channel, which is a technical means to improve carrier mobility. For example, after the sacrificial spacer is formed, a silicon germanium (SiGe) layer is selectively epitaxially grown in the cavity in the semiconductor substrate adjacent to the sacrificial spacer to form a compressive strained channel to increase hole migration. rate, or to form a silicon carbide layer to form a tensile strain channel (tensile strained channel) to increase electron mobility.

[0064] Figure 6 to Figure 8 It is shown that the temporary material layer of the present invention is used as a sacrificial spacer in the selective epitaxial growth process. First, if Figure 6 As shown, a material layer 140 is uniformly and blanketly covering the substrate 101 , the STI 102 , the gate structure 110 / 210 and the spacers 1...

no. 2 example

[0071] The temporary material layer may also be a stress providing layer in stress memorization technique (SMT). Generally speaking, this method of introducing stress into MOS transistors is the so-called stress memory technology, which usually includes the following steps: (1) performing a pre-amorphization (pre-amorphization implant, PAI) manufacturing process on the surface of the silicon substrate Forming an amorphous silicon layer; (2) then depositing a stress layer on the silicon substrate; (3) then performing a heat treatment process so that the silicon substrate can remember the stress imposed on it by the stress layer; and (4) removing stress layer.

[0072] Figure 9 to Figure 11 It shows that the temporary material layer of the present invention is used as a stress providing layer in the stress memory technology. First, if Figure 9 As shown, a pre-amorphization doping step is performed to form an amorphization region 153 . If the epitaxial material 152 is not d...

no. 3 example

[0078] figure 1 , Figure 12 to Figure 17 Another embodiment of the semiconductor device manufacturing method of the present invention is shown. In this example, there is no photoresist on the semiconductor substrate. First, if figure 1 As shown, a substrate 101 without photoresist is provided. There may be shallow trench isolation 102 in the substrate 101, there may be a gate structure 110 on the substrate 101, a first material layer 116 on the gate structure 110, and other optional components, but there is no light on the substrate 101. cause resist. The region 109 can be one of a PMOS region or an NMOS region.

[0079] The details of the gate structure 110 can refer to the previous description, which generally includes a gate dielectric layer 111, a high dielectric constant layer (not shown), a barrier layer (not shown), and a gate material layer 113 , a hard mask 115 and a first material layer 116 . For example, the layer of temporary material may be a hard mask 11...

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Abstract

The invention discloses a method for manufacturing a semiconductor component. Firstly, a gate structure on a base material and a first nitride material layer on the gate structure are provided. Secondly, a protecting step is conducted, and the first nitride material layer is modified under the oxygenated environment. Then, a second material layer is formed on the base material. Finally, a removing step is conducted after the protecting step, and a second nitride material layer is removed under the condition that the modified first nitride material layer is not reduced in effect.

Description

technical field [0001] The invention relates to a manufacturing method of a semiconductor element. In particular, it relates to a method of performing a protection step in an oxygen-containing environment to modify the first nitride material layer, and then performing a removal step to remove the modified first material layer without substantially affecting the modified first material layer. Removing a second nitride material layer prevents the first nitride material layer from being substantially slashed during the second nitride material removal step. Background technique [0002] In the existing semiconductor manufacturing process, it is hoped to increase the performance of the semiconductor device. A common method is to change the stress of the gate channel to increase the carrier mobility. New gate dielectric or gate conductive materials can also be used. [0003] But both approaches have their drawbacks. For example, it will make the manufacturing process steps more...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8238H01L21/336
Inventor 洪庆文黄志森周玲君王益昌
Owner UNITED MICROELECTRONICS CORP
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