Method for forming sidewall of semiconductor device

Abstract

The invention discloses a semiconductor device side wall forming method. The method comprises the steps of providing a semiconductor device side wall forming fore-structure, sequentially forming a first silicon oxide side wall and a first silicon nitride side wall on the two sides of a fake polycrystalline silicon grid in the side wall forming fore-structure, sequentially forming a second silicon oxide side wall and a second silicon nitride side wall outside the first silicon nitride side wall, and using a wet etching method or a wet-dry etching method to etch the surface of a device to remove a hard mask, one part of the second silicon nitride side wall, one part of the second silicon oxide side wall, one part of the first silicon nitride side wall and one part of first silicon oxide side wall. Compared with the prior art, lateral wings are prevented from erecting, the depth to width ratio of the fake polycrystalline silicon grid is reduced, a top opening of the fake polycrystalline silicon grid is larger than the bottom, gaps in a depositional interlayer medium layer are avoided, and the good condition base is established for a lateral CMP process and manufacturing of contact holes.

Description

technical field [0001] The invention relates to semiconductor manufacturing technology, in particular to a sidewall forming method in the manufacturing process of semiconductor devices. Background technique [0002] With the continuous reduction of semiconductor feature size (CD, Critical Dimension), HKMG (High-KMetalGate, high dielectric constant metal gate) and SPT (StressProximityTechnique, stress adjacent technology) have been widely used in semiconductor manufacturing processes to improve semiconductor device performance. Although the introduction of new technologies has greatly improved the performance of semiconductor devices, in the manufacturing process, due to the reduction of feature size, the size of semiconductor devices has been reduced, and the distance between gates has also been shortened, which has brought new problems that need to be solved. Problems affecting device quality and performance. [0003] figure 1 Shown is a schematic diagram of an existing ...

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Problems solved by technology

from figure 2 It can be seen from the figure that since the materials of the hard mask 3 and the silicon nitride spacer 13 on the upper part of the dummy polysilicon gate 2 are all made of silicon nitride, the H 3 PO 4 After the solution removes the silicon nitride, the hard mask 3 and the silicon nitride spacer 13 on the upper part of the dummy polysilicon gate 2 will be partially etched, but in the NMOS region, due to the H 3 PO 4 The etching rate of the solution to silicon oxide is much lower than that of silicon nitride, and the thickness range of the silicon oxide sidewall 12 in the prior art is 40-80 angstroms to effectively protect the pseudo-polysilicon gate 2, so the silicon oxide sidewall The etching of the wall 12 is much smaller than the hard mask 3 of silicon nitride material and the silicon nitride sidewall 13, so the silicon oxide sidewall 12 is higher than the etched hard mask 3, and then in the NMOS region A stickup shoulder 5 (the dotted line area in the figure) appears in the dummy gate structure, and the stickup shoulder 5 will affect the deposition and chemical mechanical polishing (CMP) of the interlayer dielectric layer (ILD, InterLayer Dielectric) in the later stage. In turn, it will also affect the subsequent formation of the metal gate for the following reasons

[0005] Because as the feature size shrinks, the distance between the gates is also becoming smaller, and the vertical side wings 5 ​​on both sides of the dummy gate structure make the aspect ratio of the space between the dummy gate structures larger, and then as image 3 As shown, when the interlayer dielectric layer 6 is formed, a void 61 will be generated in the interlayer dielectric layer 6 between the dummy gate structures, and the appearance of the void 61 will affect the subsequent processing of the interlayer dielectric layer 6 In the CMP process, the surface morphology of the device after CMP will become uneven, which will also affect the preparation of the metal gate, and may also reduce the performance of the manufactured semiconductor device.

[0006] However, in the prior art, if the erected flank 5 is to be removed, it is necessary to further etch the erected flank 5 by means of etching (such as a wet etching method), but in the process of etching, it is inevitable that the Over-etching occurs on other parts of the device surface, such as over-etching the substrate on both sides of the pseudo-polysilicon gate structure, thereby causing damage to the substrate, or destroying the metal silicide (such as NiSi) formed on the substrate surface, affecting the semiconductor Conductivity of the device

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