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Packaging structure and forming method thereof

A packaging structure, dry deglue technology, applied in the direction of electrical components, electrical solid devices, circuits, etc., can solve the problems of reliability failure, low reliability of packaging structure stability, etc., to achieve improved stability, improved mechanical strength, Good adhesion effect

Active Publication Date: 2014-03-12
CHINA WAFER LEVEL CSP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, the stability and reliability of the packaging structure formed by the prior art is low, and there is a risk of reliability failure

Method used

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  • Packaging structure and forming method thereof
  • Packaging structure and forming method thereof
  • Packaging structure and forming method thereof

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0043] Figure 3 to Figure 8 is a schematic cross-sectional structure diagram of the forming process of the package structure in the first embodiment of the present invention.

[0044] Please refer to image 3 , providing a chip layer 201, the first surface 1 of the chip layer 201 has a protection layer 203, the surface of the protection layer 203 has a pad layer 202, the surface of the protection layer 203 and the pad layer 202 has a substrate 200, the The second surface II of the chip layer 201 has several grooves 204 exposing the protective layer 203, the second surface II of the chip layer 201 is opposite to the first surface I, and the position of the grooves 204 is the same as that of the pad layer 202. correspond.

[0045] The chip layer 201 is a substrate on which semiconductor devices are formed, and the substrate is a silicon substrate, a silicon-germanium substrate, a silicon carbide substrate, a silicon-on-insulator substrate, a germanium-on-insulator substrate, ...

no. 2 example

[0084] Figure 9 is a schematic cross-sectional structure diagram during the formation process of the package structure of the second embodiment of the present invention.

[0085] In the first embodiment Figure 5 Based on that, please continue to refer to Figure 9 , using a plasma etching process to remove part of the first insulating layer 208 around the through hole 209 (such as Figure 5 shown) and protection layer 203 (as Figure 5 As shown), the first insulating layer 208b and the protective layer 203b are formed, and part of the pad layer 202 at the bottom of the trench 204 is exposed, so that the thickness of the first insulating layer 208b and the protective layer 203b becomes thinner as it gets closer to the through hole 209 , and the surface of the passivation layer 203 b at the bottom of the trench 204 is inclined relative to the surface of the pad layer 202 .

[0086] The process of removing part of the first insulating layer 208 and the protective layer 203 ...

no. 3 example

[0100] Figure 10 is a schematic cross-sectional structure diagram during the formation process of the packaging structure of the third embodiment of the present invention.

[0101] In the first embodiment Figure 6 Based on that, please continue to refer to Figure 10 , using the plasma dry deglue process to remove part of the first insulating layer 208 around the through hole 209 (such as Figure 5 After that, part of the first insulating layer 208 and the protective layer 209 around the through hole 209 are removed by plasma etching process, forming the first insulating layer 208c and the protective layer 209c, and exposing the part of the bottom of the trench 204 For the pad layer 202 , the protection layer 209 c becomes thinner as it gets closer to the through hole 209 , and the surface of the protection layer 209 c at the bottom of the trench 204 is inclined relative to the surface of the pad layer 202 .

[0102] In this embodiment, first, a part of the first insulati...

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Abstract

The invention discloses a packaging structure and a forming method thereof, wherein the forming method of the packaging structure is that the first surface of a chip layer is provided with a protective layer and a welding pad layer, and the second surface of the chip layer is provided with a plurality of grooves exposed out of the protective layer; a first insulation layer is formed at each of the second surface of the chip layer, and the surfaces of the side walls and the bottoms of the grooves; the thicknesses of the first insulation layers positioned at the bottoms of the grooves are thinner than the thickness of the first insulation layer positioned at the second surface of the chip layer; through holes penetrating through the first insulation layers, the protective layer and the welding pad layer are formed in the bottoms of the grooves; parts of the first insulation layers around the through holes are removed and are exposed out of the bottoms of the grooves; afterwards, conductive layers are formed at the surfaces of the first insulation layers, the surfaces of the bottoms of the grooves, and the surfaces of the side walls and the bottoms of the through holes. The electrical performance and the stability of the formed packaging structure are improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a packaging structure and a forming method thereof. Background technique [0002] Wafer Level Chip Size Packaging (WLCSP) technology is a technology in which a wafer is packaged and tested and then cut to obtain a single finished chip. The size of the packaged chip is exactly the same as that of the bare chip. Wafer-level chip-scale packaging technology has completely subverted traditional packaging, such as ceramic leadless chip carrier (Ceramic Leadless Chip Carrier) and organic leadless chip carrier (Organic Leadless Chip Carrier), etc. , small, short, thin and low-cost requirements. The size of the chip packaged by the wafer-level chip size packaging technology can be highly miniaturized, and the cost of the chip is significantly reduced with the reduction of the chip size and the increase of the wafer size. Wafer-level chip-scale packaging technology is...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/31H01L21/50
CPCH01L2224/11
Inventor 王之奇喻琼王蔚
Owner CHINA WAFER LEVEL CSP
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