Silicide Formation Method

Abstract

A formation method of silicide is provided. The formation method includes the following steps that: a substrate is provided; side walls are formed at two sides of a gate dielectric layer, a gate electrode layer and a first mask layer at the surface of the substrate; first sacrificial layers are formed on the surface of the substrate; the first mask layer is removed, grooves are formed between the top surface of the gate electrode layer and the side walls; a second sacrificial layer coating the top surface of the gate electrode layer and groove side walls is formed in the grooves, and the width of the second sacrificial layer located at the groove side walls is uniform; a second mask layer is formed on the surface of the second sacrificial layer, and the grooves are filled with the second mask layer; with the second mask layer adopted as a mask, the second sacrifice layer and the gate electrode layer are etched until part of the gate electrode layer with a certain thickness is removed; and a silicide layer is formed on the surface of the gate electrode layer of which part with a certain thickness is removed. With the formation method of the silicide adopted, the superficial area of the formed gate electrode layer is increased, and the degradation of the resistance of the gate electrode layer can be benefitted, and operating rate of a device can be improved.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, and in particular, to a method for forming silicide. Background technique [0002] With the continuous development of CMOS technology, sub-micron devices have been widely used. However, due to the fine gate and source / drain contact regions formed in sub-micron MOS devices, the contact resistance and sheet resistance increase. This greatly reduces the operating speed of semiconductor devices. [0003] The salicide formation process can effectively reduce sheet resistance and contact resistance by forming silicide in the gate and source / drain regions. The formation process of self-aligned silicide in the prior art is mainly to form a metal layer on the surface of polysilicon through evaporation or sputtering process; annealing treatment, the metal reacts with polysilicon to form metal silicide; and the unreacted metal layer is removed. [0004] For more information on the formatio...

AI Technical Summary

Problems solved by technology

However, contact resistance and sheet resistance increase due to the small gate and source / drain contact areas formed in sub-micron MOS devices

This makes the operating speed of semiconductor devices greatly reduced

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