A lateral soi power ldmos device
A lateral, power technology, applied in the direction of semiconductor devices, electrical components, circuits, etc., can solve the problem of depending on, achieve the effect of reducing gate leakage current
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Embodiment 1
[0033] figure 2 It is the N-channel lateral SOI power LDMOS provided by the present invention, and its structure is as follows figure 2 As shown, it includes a substrate layer 1, a dielectric buried layer 2, and an active layer vertically from bottom to top; the active layer has a P-type body region 5 on one side in the lateral direction (x direction shown in the figure), and the P-type The surface of the body region 5 has an adjacent N-type source region 6 and a P-type body contact region 7, and the surfaces of the N-type source region 6 and the P-type body contact region 7 are connected to the metallized source S; The other side has an N-type drain region 8, the surface of the drain region 8 is connected to the metallized drain D; the surface of the P-type body region 5, including a part of the N-type source region 6 connected thereto, has a gate dielectric 3, The gate dielectric 3 has a gate conductive material 4 on its surface, and the gate conductive material 4 is conn...
Embodiment 2
[0036] image 3 It is an N-channel lateral SOI power LDMOS with a buffer layer provided by the present invention, such as image 3 As shown, compared with Example 1, the N-type drift region 9 has an N-type buffer layer 9a, the buffer layer 9a is located at the upper interface of the dielectric buried layer 2, and its doping concentration is higher than that of the N-type drift region 9 doping concentration. According to the one-dimensional Poisson's equation and Gauss' theorem, the buffer layer 9a can increase the electric field at the interface between the active layer and the buried dielectric layer 2, thereby increasing the electric field in the buried dielectric layer 2 and improving the withstand voltage of the device.
Embodiment 3
[0038] Figure 4 It is an N-channel lateral SOI power LDMOS with a grooved gate provided by the present invention. Compared with Embodiment 1, this example has a grooved gate structure, and the grooved gate structure is located in the P-type body region 5, and the peripheral gate dielectric 3 It is composed of a gate conductive material 4; the slot gate structure is embedded in the P-type body region 5 in a columnar shape, and is adjacent to the N-type source region 6; The introduction of the trench gate forms a vertical channel in the P-type body region 5, which forms a three-dimensional channel with the planar channel, increases the channel current density, reduces the channel resistance, and further reduces the specific on-resistance. Figure 4 On the left is a cross-sectional view of the trench gate structure along the yz plane.
[0039] The semiconductor high resistance region 12 in the above embodiments is N-type or P-type.
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