Preparation method of dual contact hole etching stop layer

Abstract

The invention provides a preparation method of a dual contact hole etching stop layer. The preparation method comprises the steps of 01, providing an MOS device, depositing a tensile stress silicon nitride layer on the MOS device as a contact hole etching stop layer and carrying out ultraviolet light polymerization treatment on the tensile stress silicon nitride layer; 02, coating the tensile stress silicon nitride layer with a photoresist layer; 03, carrying out exposure and development on the photoresist layer, removing the part, in the PMOS area of the MOS device, of the photoresist layer and retaining the part, in the NMOS area of the MOS device, of the photoresist layer; 04, carrying out ion implantation on the part, in the PMOS area of the MOS device, of the silicon nitride layer to form a pressure stress silicon nitride layer; 05, removing the part, in the NMOS area of the MOS device, of the photoresist layer. Compared with a traditional preparation process for the dual contact hole etching stop layer, the preparation method is simpler and lower in cost, thereby having the significant advancement of improving the device performance at a low cost.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuit manufacturing, and more specifically, to a preparation method of an etching stop layer for double contact holes based on strained silicon technology. Background technique [0002] With the development of CMOS integrated circuit manufacturing process and the reduction of critical dimensions, many new methods have been applied to device manufacturing process to improve device performance. The high-stress silicon nitride film is introduced into the integrated circuit manufacturing process because it can effectively improve the carrier mobility of the MOS tube, thereby increasing the operating speed of the device. The compressive stress in the direction of the PMOS channel can improve the hole mobility in the PMOS device, and the tensile stress in the direction of the NMOS channel can improve the electron mobility in the NMOS device. [0003] see figure 1 , figure 1 It is a...

AI Technical Summary

Problems solved by technology

Since two-step photolithography is required in the traditional Dual CESL process to remove high-tensile-stress silicon nitride in the PMOS region and high-voltage-stress silicon nitride in the NMOS region, this process greatly increases process cost and process complexity

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