A Successive Approximation Analog-to-Digital Converter for Monotonic Switching Mode
A successive approximation, analog-to-digital converter technology, applied in the direction of analog/digital conversion, code conversion, instruments, etc., can solve comparator offset, SARADC power consumption, large fluctuations in speed and accuracy, and reduce the effective resolution of the system, etc. problem, to achieve the effect of fast speed, low power consumption and stable performance
Inactive Publication Date: 2017-05-10
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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However, due to the limitations of the process and circuit, there are comparator offset and noise errors in the SAR ADC, which will reduce the effective resolution of the system. In the monotonic switching mode, the power consumption, speed, and accuracy of the SAR ADC fluctuate greatly, resulting in The analog-to-digital converter works unstable
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[0023] Specific embodiments of the present invention will be described below in conjunction with the accompanying drawings, so that those skilled in the art can better understand the present invention. It should be noted that in the following description, when detailed descriptions of known functions and designs would dilute the main content of the present invention, these descriptions will be omitted here.
[0024] figure 1 It is the SAR ADC structure and timing diagram based on offset and noise error tolerance technology, including two parts: the upper part is the structure diagram of SAR ADC and the lower part is the working timing diagram of SAR ADC. The SAR ADC structure diagram shows the relationship between the charge redistribution DAC, comparator and control logic of n-bit SAR ADC. where the capacitance value of the DAC is determined by the formula above the array, C m and C m+1 Capacitance values are equal. Bits n-m are the redundant compare period. The timing...
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The invention discloses a successive approximation analog-to-digital converter used in a monotone switching mode, which belongs to the field of high-speed successive approximation analog-to-digital converters, in particular to the field of comparator circuits. Including: charge redistribution digital-to-analog converter, comparator, control logic unit. Add a redundant circuit to the charge redistribution digital-analog converter in the existing analog-to-digital converter, and add a tail current source that can be controlled by logic to the existing comparator, and adjust the ratio of the tail current in different comparison periods The adjustment to the offset and noise of the comparator has the advantages of simple structure, low power consumption and high speed. The 10-bit 100MS / s verified successive approximation analog-to-digital converter designed in the 0.13μm process can obtain more than 9.3 effective bits, the power consumption is only 1.7mW, and the quality factor can reach 25.7fJ / conv.
Description
technical field [0001] The invention relates to the circuit structure of a high-speed successive approximation (SAR) analog-to-digital converter (ADC) and the design and realization of a comparator circuit, as well as a tolerance algorithm for SAR ADC offset and noise errors. Background technique [0002] ADC is an indispensable module in communication, digital signal processing and other systems. At the same time, with the gradual development and popularity of consumer electronics, handheld devices and biomedical devices, and the development of battery technology lagging behind electronic technology, the requirements for sustainability and low power consumption of electronic devices are gradually increasing. Therefore, the development of ADC chips with high performance and low power consumption is the development direction and trend in recent years. [0003] With the advancement of integrated circuit technology, the power supply voltage must be reduced, and the intrinsic g...
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IPC IPC(8): H03M1/38
Inventor 高俊枫李广军
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA