Semiconductor device formation method

Abstract

The invention relates to a semiconductor device formation method. The semiconductor device formation method comprises steps that a substrate is provided, the substrate has a first active region and a second active region, and the first active region and the second active region have opposite types; a first dummy grid electrode structure at the first active region and a second dummy grid electrode structure at the second active region are formed on the substrate, the first dummy grid electrode structure comprises a first grid medium layer and a first dummy grid electrode, and the second dummy grid electrode structure comprises a second grid medium layer and a second dummy grid electrode; an interlayer dielectric layer is formed on the substrate, and the upper surface of the interlayer dielectric layer is level with the upper surface of the first dummy grid electrode and the upper surface of the second dummy grid electrode; the first dummy grid electrode is removed to form a first dummy grid slot; the second dummy grid electrode is removed to form a second dummy grid slot; third grid dielectric layers are formed at the bottom portion and side walls of the second dummy grid slot. According to the semiconductor device formation method, parameters of material composition and thickness of the first grid dielectric layer and the third grid dielectric layers can be respectively adjusted, and thereby performance of transistors of the corresponding first grid dielectric layer and the third grid dielectric layers is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for forming a semiconductor device. Background technique [0002] In the prior art, metal gate transistors using a high-K gate dielectric layer are generally accepted. Compared with traditional CMOS transistors, metal transistors using high-K gate dielectric layers can reduce gate leakage current, improve time-dependent dielectric breakdown (Time Dependent Dielectric Breakdown, TDDB) performance, and reduce the probability of gate dielectric layer breakdown. possibility. [0003] Figure 1 ~ Figure 3 It is a schematic cross-sectional structure diagram of a method for simultaneously forming a PMOS metal transistor and an NMOS metal transistor on the same substrate in the prior art. [0004] refer to figure 1 , the substrate 100 includes a P-type active region and an N-type active region, and a first high-K gate dielectric layer 101 and a first dummy gate locate...

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Problems solved by technology

[0008] The problem solved by the present invention is the process of simultaneously forming PMOS metal transistors and NMOS metal transistors on the same substrate, and the formed NMOS metal transistors have poor performance

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