Semiconductor contact hole etching method

Abstract

The invention relates to a semiconductor contact hole etching method achieved through a sandwich structure. The method includes the steps of providing a substrate, wherein a plurality of electric conduction structures are formed on the substrate; forming a first SiN layer covering the substrate and the electric conduction structures on the substrate; forming an SiO2 layer on the first SiN layer; forming a second SiN layer on the SiO2 layer; forming an ILD layer of the SiO2 layer on the second SiN layer through deposition; flattening the ILD layer and forming an ILD cap layer on the surface of the ILD layer, wherein the ILD cap layer sequentially comprises a photoetching adhesive layer and an anti-reflection coating from top to bottom; forming a contact hole pattern in the photoetching adhesive layer; conducting etching through the contact hole pattern so that all the electric conduction structures and source/drain electrodes located on the two sides of the electric conduction structures can be exposed. The method has the advantages that the adoption of the single-medium SiN or double-layer media is avoided, and the number of silicon oxides on the surface of the substrate and the number of consumed STI layers are decreased.

Description

technical field [0001] The present invention relates to the field of semiconductor manufacturing. Specifically, it relates to an etching method using a semiconductor material with a sandwich structure as an etching stop layer for a contact hole. Background technique [0002] The choice of etch stop layer for contact hole etching is mostly a single dielectric SiN layer. There are also cases in the industry where SiON or SiN-SiON composite layers are used instead of SiN due to high requirements for leakage. Whether it is SiN or SiON-SiN composite etch barrier layer, under the pressure of Moore's law on the chip area, its thickness becomes smaller with the channel length, so that the interlayer dielectric layer (ILD) to the contact hole The selection ratio of the etch stop layer (CESL) puts forward higher requirements, but whether the photolithography scheme such as PR (photoresist) or HM (hard mask) is used, the interlayer dielectric layer (ILD) is the most important for cont...

AI Technical Summary

Problems solved by technology

Whether it is SiN or SiON-SiN composite etch barrier layer, under the pressure of Moore's law on the chip area, its thickness becomes smaller with the channel length, so that the interlayer dielectric layer (ILD) to the contact hole The selection ratio of the etch stop layer (CESL) puts forward higher requirements, but whether the photolithography scheme such as PR (photoresist) or HM (hard mask) is used, the interlayer dielectric layer (ILD) is the most important for contact hole etching. There is a limit to the improvement of the selectivity ratio of the layer (CESL), so when there is a process miss in the current layer, such as excessive lithography deviation or insufficient metal silicide thickness, it will affect the shallow trench isolation structure (STI) and the bottom The silicide layer causes greater loss, which affects the corresponding parameters such as breakdown voltage and contact resistance, causing device failure

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