Array substrate and preparation method thereof

Abstract

The invention discloses an array substrate and a preparation method thereof. The array substrate comprises a substrate, a buffer layer, a semiconductor pattern layer, a first grid electrode insulation layer, a second grid electrode insulation layer, a first conductive pattern layer, an interlayer insulation layer and a second conductive pattern layer, wherein the substrate comprises a thin-film transistor region and a capacitor region; the buffer layer is formed on the substrate; the semiconductor pattern layer is formed on the buffer layer and comprises a source and drain electrode region and a first electrode; the first grid electrode insulation layer is formed on the semiconductor pattern layer and correspondingly covers regions, except the first electrode, of the thin-film transistor region and the capacitor region; the second grid electrode insulation layer is formed on the first grid electrode insulation layer; the first conductive pattern layer is formed on the second grid electrode insulation layer and comprises a grid electrode and a second electrode; the interlayer insulation layer is formed on the first conductive pattern layer; the second conductive pattern layer is formed on the interlayer insulation layer and comprises a source electrode and a drain electrode which are coupled with the source and drain electrode region as well as a third electrode. With the adoption of the array substrate and the preparation method thereof, the capacitance of a capacitor is increased, film layer structures of the regions except the capacitor region are not changed, the signal line load is effectively decreased, and meanwhile, short-circuit risks of upper and lower film layers of the grid electrode insulation layers are reduced.

Description

technical field [0001] The invention relates to a low-temperature polysilicon (LTPS) array substrate and a preparation method thereof, in particular to an array substrate capable of effectively increasing capacitance and a preparation method thereof. Background technique [0002] In recent years, people have higher and higher requirements for the resolution of the display, and correspondingly, the space for wiring in the pixel is getting smaller and smaller. The capacitance in the pixel directly affects the electrical characteristics of the pixel and then affects the display characteristics. Therefore, the improvement in the limited layout space The capacitance value in the pixel is particularly important. [0003] Such as figure 1 , figure 2 As shown, it is a cross-sectional view of the film layer structure of capacitors and thin film transistors formed on an array substrate in a conventional way. figure 1 It includes a glass substrate 11, which is divided into a thin f...

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Problems solved by technology

[0005] use figure 2 Although the method shown can increase the capacitance value, it still cannot meet the design requirements as the pixel size decreases

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