Back-passivation efficient PERL battery technology
A process and battery technology, applied in the field of high-efficiency PERL battery technology with back passivation, can solve the problems of unstable process, difficult removal of borosilicate glass phase, cross-doping, etc., and achieve the goal of simplifying the process flow, reducing production costs and reducing dosage Effect
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[0029] Example 1
[0030] A back passivation high-efficiency PERL battery process, the process is as follows figure 1 As shown, the following steps are taken:
[0031] Step 1: The original silicon wafer is cleaned in HF / HNO3 mixed solution to remove the surface damage layer, cutting line marks, etc.;
[0032] Step 2: Polish the above-mentioned silicon wafer on both sides in NaOH solution;
[0033] Step 3: Deposit SiOx on one side of the polished silicon wafer. High temperature thermal oxidation, PECVD or APCVD can be used to deposit SiOx film on one side, and then annealed at 400°C for densification;
[0034] Step 4: Prepare the 1-2um high pyramid suede on one side of the silicon wafer in TMAH;
[0035] Step 5: The above-mentioned silicon wafers are deposited and diffused in single-sided POCL3 in a high-temperature furnace;
[0036] Step 6: Use wet etching equipment to remove surface phosphosilicate glass (PSG);
[0037] Step 7: Deposit SiNx with a thickness of about 80nm on the front sid...
Example Embodiment
[0044] Example 2
[0045] A back-passivation high-efficiency PERL battery process. The process is the same as that of Embodiment 1, except that in step (3), a SiNx dielectric layer is deposited on a single side of the polished silicon wafer. Step (8) deposit a SiOx dielectric layer on the backside of the polished surface of the silicon wafer.
Example Embodiment
[0046] Example 3
[0047] A back-passivation high-efficiency PERL battery process. The process is the same as that of Embodiment 1, except that step (3) deposits an a-Si dielectric layer on a single side of the polished silicon wafer. Step (8) deposit an a-Si dielectric layer on the backside of the polished surface of the silicon wafer.
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