A kind of HKMG device and preparation method thereof
A device and substrate technology, applied in the field of HKMG devices and their preparation, can solve the problems of electrical parameter degradation, which cannot completely solve the short channel effect of HKMG devices, and the degradation of electrical parameters of PFET devices, so as to achieve low threshold voltage and suppress short Channeling effect, improving the effect of electrical parameter degradation
Active Publication Date: 2018-03-02
SEMICON MFG INT (SHANGHAI) CORP
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Problems solved by technology
[0004] In order to solve the above problems, in the traditional process, the ultrathin-body structure (UTB) is used to suppress the short channel effect (SCE) of the low-threshold voltage (low-Vt) NBEM device, or by using SiGe material To adjust the channel work function of PFETs (p-channel field effect transistors) to obtain a low threshold voltage; but the above-mentioned processes cannot completely solve the short channel effect of HKMG devices, especially PFET devices will also be affected by negative bias temperature Instability (negative bias temperature instability, referred to as NBTI) caused electrical parameter degradation
[0005] In the actual production process, it is found that none of the existing technical solutions can completely solve the short channel effect of HKMG devices, especially the PFET devices will also cause electrical parameter degradation due to negative bias temperature instability.
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[0058] Figure 2-8 It is a schematic flow chart structure diagram of an embodiment of a preparation method of a HKMG device of the present application; as Figure 2-8 As shown, a preparation method of a HKMG device, preferably, the method can be applied in the process of 65nm and below technology nodes, and the above-mentioned method is based on the flattening of the interlayer dielectric layer in the gate-last (gate-last) process Based on the semiconductor structure formed after the ILD CMP step, the method specifically includes:
[0059] First, the sample gate preparation process is carried out on a silicon (Silicon) substrate by using the gate-last process, and the planarization process (preferably, chemical mechanical polishing can be used) of the interlayer dielectric layer (Inter Layer Dielectrics, referred to as ILD) process (Chemical Mechanical Polishing, referred to as CMP) to perform the planarization process of the interlayer dielectric layer) step, the formation o...
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The present invention relates to the technical field of semiconductor manufacturing, in particular to an HKMG device and a preparation method thereof. During the gate-last process, on the basis of the device structure formed in the interlayer dielectric layer planarization process step, the sample gate is removed first, Then continue to coat the deep ultraviolet absorbing oxide material layer, and use photolithography and etching processes to etch the deep ultraviolet absorbing oxide material layer in the PFET device area into the substrate to partially etch the substrate to form a substrate groove, And after continuing to grow the SiGe layer, Si layer and insulating layer in the substrate groove, continue the subsequent double metal gate process on the upper surface of the insulating layer to finally form a MOSFET device with a SiGe channel; using the above process The prepared MOSFET can effectively suppress the short channel effect of the HKMG device while providing a low threshold voltage that meets the process requirements.
Description
technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to an HKMG device and a preparation method thereof. Background technique [0002] At present, as the size of MOSFET tends to be miniaturized, low leakage (low leakage) high dielectric constant dielectric metal gate (High-K Metal Gate, HKMG for short) technology is widely used in MOSFET, but due to the gate and channel The not band edge-matched (NBEM for short) makes the MOSFET device prepared by HKMG technology able to provide a lower threshold voltage (low threshold voltage), but also produces serious short channel Channel effect (short-channel effects, referred to as SCE). [0003] In the actual production process, the above-mentioned problems will not only occur in single-metal-gate technologies (that is, MOSFETs prepared by HKMG technology will also have serious SCE problems while providing low threshold voltage), Moreover, the above-mentioned short channel...
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IPC IPC(8): H01L27/092H01L29/78H01L21/8238H01L21/336
Inventor 倪景华李凤莲
Owner SEMICON MFG INT (SHANGHAI) CORP