A kind of Sonos dual-gate flash memory device and compiling method thereof

Abstract

The invention discloses a SONOS dual-gate flash memory device, which comprises a P-type substrate having two ends of an N-type source and drain, and a first polysilicon gate, a first control gate, and a second polysilicon gate respectively located on the upper and lower sides of the substrate in parallel. The silicon gate and the second control gate are respectively provided with the first and second silicon nitride layers between the first and second control gates and the substrate; when compiling, the first and second polysilicon gates are connected, and the The gate voltage is equal to the threshold voltage of the device, connect the first and second control gates, apply the same control gate voltage higher than the threshold voltage of the device, apply a positive voltage to the drain terminal, and apply a 0V voltage to the source terminal, so that the first 1. A thinner channel electron layer is induced in the substrate region under the second polysilicon gate, and a thicker channel electron layer is induced in the substrate region under the first and second control gates, and the acceleration effect of the positive voltage at the drain terminal Under the condition, the electrons in the thinner channel electron layer are accelerated to generate hot electrons, which are injected into the first and second silicon nitride layers under the action of the high voltage of the control gate to complete compilation.

Description

technical field [0001] The invention relates to the technical field of semiconductors, and more specifically, to a SONOS dual-gate flash memory device and a compiling method thereof. Background technique [0002] SONOS (Silicon-Oxide-Nitride-Oxide-Silicon, Silicon-Oxide-Nitride-Oxide-Silicon) is a non-volatile memory that is closely related to flash memory. The main difference between it and mainstream flash memory is that it uses silicon nitride instead of polysilicon as the storage material. A branch of SONOS is SHINOS (Silicon-High Dielectric-Nitride-Oxide-Silicon). SONOS allows lower programming voltage and higher program-erase cycles than polysilicon flash memory, and is a relatively active research and development hotspot. SONOS flash has data retention advantages over floating-gate flash, allowing it to use a thinner oxide layer and retain information longer. [0003] The US patent publication No. US5300803A discloses a non-volatile memory structure whose compiling...

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Problems solved by technology

[0006] The problem with the split-gate floating-gate flash memory structure disclosed in this patent is that due to the relatively high voltage (5v) applied to the drain terminal, the width of the depletion layer extending from the drain terminal to the substrate is relatively large, and the source terminal and the virtual depletion layer regions can easily touch together at high voltages, causing device punch-through and failure

We all know that due to the short channel effect, when the size of the MOSFET is shortened, the subthreshold slope will become smaller, causing the device to turn off continuously and the leakage current to be large

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