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Quality optimizing method of silicon epitaxial layer HBT base region in BiCOMS technology

A germanium-silicon epitaxy and process method technology, which is applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems affecting device performance, damage, affecting the quality of germanium-silicon epitaxial layers, etc. The effect of improving quality

Active Publication Date: 2015-10-21
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In the existing process, before the formation of the silicon germanium epitaxial layer (EPI) in the HBT region, a thin gate oxide is formed on the surface of the active region of the silicon germanium epitaxial layer formation region used as the base region, and during the etching process of the polysilicon gate The thin gate oxide is not easy to form a good protection on the surface of the active region at the bottom, so that the surface of the active region in the formation region of the silicon germanium epitaxial layer will be damaged, thereby affecting the quality of the subsequent silicon germanium epitaxial layer and affecting the performance of the device

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  • Quality optimizing method of silicon epitaxial layer HBT base region in BiCOMS technology
  • Quality optimizing method of silicon epitaxial layer HBT base region in BiCOMS technology
  • Quality optimizing method of silicon epitaxial layer HBT base region in BiCOMS technology

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Embodiment B

[0025] Such as figure 1 Shown is the flow chart of the method of the embodiment of the present invention; Figure 2A to Figure 2D Shown is a device structure diagram in each step of the method of the embodiment of the present invention. In the BiCMOS process of the embodiment of the present invention, in the quality optimization process method of the HBT base silicon germanium epitaxial layer 110, the BiCMOS process integrates HBT and CMOS devices with two operating voltages in the same silicon substrate 101, and the two operating voltages are respectively the first operating voltage. and a second operating voltage, wherein the first operating voltage is greater than the second operating voltage; in an embodiment of the present invention, the first operating voltage is 3.3V, and the second operating voltage is 1.8V, including the following steps:

[0026] First, if Figure 2A As shown, a field oxygen layer 102 is formed in the silicon substrate 101. The field oxygen layer 10...

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Abstract

The invention discloses a quality optimizing method of a silicon epitaxial layer HBT base region in BiCOMS technology. The quality optimizing technology comprises steps of forming a first gate oxide layer; etching the first gate oxide layer; forming a second gate oxide layer whose thickness is smaller than the thickness of the first gate oxide layer; generating and photoetching a first polycrystalline silicon layer so as to form polysilicon gate; generating and photoetching an SC film so as to form a germanium-silicon window; performing thermal oxide growth and wet-process removing so as to eliminate defects of the silicon substrate surface in the germanium-silicon window area; and performing a germanium-silicon epitaxial layer. According to the invention, after the germanium-silicon window is formed, the thermal oxidation and wet-process removing are performed to remove an oxide layer to eliminate the defects of the silicon substrate surface in the germanium-silicon window area, thereby eliminating damage of the active area surface of a germanium-silicon epitaxial layer forming area in the base region, improving quality of the germanium-silicon epitaxial layer in the HBT base and improving the HBT performance.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit manufacturing process method, in particular to a process method for optimizing the quality of the silicon germanium epitaxial layer in the HBT base area in the BiCMOS process. Background technique [0002] The BiCMOS process is a process that simultaneously integrates complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) and bipolar junction transistor (Bipopar Junction Transistor, BJT) devices on the same chip. A junction bipolar transistor (Heterojunction Bipolar Transistor, HBT) generally uses a silicon germanium epitaxial layer as a base region, and has better frequency characteristics. Therefore, in the existing BiCMOS process, there will be CMOS devices and HBT devices coexisting. CMOS devices include NMOS devices and PMOS devices. Therefore, how to integrate these two devices without affecting each other's characteristics has become an important issue t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8249H01L21/331
CPCH01L21/8249H01L29/66242
Inventor 陈曦周正良
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP