A Method for Reducing Threshold Voltage Fluctuation of High-k Metal Gate Devices

Abstract

The invention relates to the field of semiconductors, and particularly relates to a method for reducing high K metal gate device threshold voltage fluctuation. According to the method for reducing high K metal gate device threshold voltage fluctuation, the method comprises the steps that a substrate is provided, a PMOS region and an NMOS region are formed on the substrate, and the PMOS region and the NMOS region respectively comprise a high K dielectric layer; titanium nitride (TiN) is deposited on the high K dielectric layer of the PMOS region and the NMOS region; a silicon film is deposited on the PMOS region and the NMOS region to act as a barrier layer, and then a P-type function layer is deposited on the barrier layer; the P-type function layer and the silicon film of the NMOS region are removed in turn; and the annealing technology is performed on the PMOS region.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a method for reducing threshold voltage fluctuations of high-K metal gate devices. Background technique [0002] As the integration of semiconductor devices becomes higher and higher, the requirements for the size of semiconductor devices become smaller and smaller. At the time of ultra-deep submicron level, such as 45 nanometers and below technology nodes, the channel length in MOSFET The reduction of the thickness of the gate oxide and the thinning of the gate oxide layer will bring high leakage, which will cause the shift of the threshold voltage. [0003] In the high-k metal-gate semiconductor process, tantalum nitride (TaN) is usually selected as the barrier layer for the removal of the P-type work function layer TiN in the NMOS region, and the TiN etching process itself will have certain fluctuations, which will cause as The fluctuation of the remaining TaN thickness of the b...

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Problems solved by technology

[0002] As the integration of semiconductor devices becomes higher and higher, the requirements for the size of semiconductor devices become smaller and smaller. At the time of ultra-deep submicron level, such as 45 nanometers and below technology nodes, the channel length in MOSFET The reduction of the thickness of the gate oxide and the thinning of the gate oxide layer will bring high leakage, which will cause the shift of the threshold voltage

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