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A method of forming a metal interconnect structure

A technology of metal interconnect structure and metal hard mask layer, which is applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc. Large and other problems, to achieve the effect of reducing polishing time, reducing thickness difference, and reducing thickness difference

Active Publication Date: 2018-08-21
SEMICON MFG INT (SHANGHAI) CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] figure 1 It is a schematic diagram of a conventional method for forming a copper interconnection structure through a CMP process. First, a first grinding process is performed to remove excess copper 11 outside the trench, and the grinding process ends at the diffusion barrier layer 12; and then a second grinding process is performed. , grinding and removing the multi-layer thin film material layers including the diffusion barrier layer 12 outside the trench, the metal hard mask layer 13, the oxide hard mask layer 14, and a small amount of low-K dielectric layer 15, due to the second grinding In the process, the multi-layer thin film material layer needs to be ground and removed. The grinding process is complex and changeable, and the grinding time is long, so that after the entire CMP process is completed, different positions on the wafer surface, especially the low-K dielectric layer and trenches at different positions The thickness of the copper in the slots can vary widely, reducing wafer performance and stability

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  • A method of forming a metal interconnect structure
  • A method of forming a metal interconnect structure
  • A method of forming a metal interconnect structure

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[0026] In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention.

[0027] For a thorough understanding of the present invention, a detailed description will be presented in the following description to explain the method of manufacturing the semiconductor device of the present invention. Obviously, the practice of the invention is not limited to specific details familiar to those skilled in the semiconductor arts. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments besides these detailed descriptions.

[0028] It should be noted that the terms...

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Abstract

The invention provides a method for forming a metal interconnection structure. The method comprises the following steps of providing a semiconductor substrate, a low-K dielectric layer, an oxide hard mask layer and a metal hard mask layer, wherein grooves are formed in the low-K dielectric layer, the oxide hard mask layer and the metal hard mask layer, and a diffusion barrier layer and a metal layer are formed in the grooves and on the metal hard mask layer; executing first chemical mechanical grinding to remove a metal layer outside the grooves and stopping in the diffusion barrier layer; executing second chemical mechanical grinding to remove the diffusion barrier layer outside the grooves and stopping in the metal hard mask layer; etching to remove the metal hard mask layer to make the oxide hard mask layer exposed; and executing third chemical mechanism grinding to remove the oxide hard mask layer, and forming the metal interconnection structure. According to the method for forming the metal interconnection structure, provided by the invention, the thickness difference of a wafer surface obtained by final grinding at different positions is reduced.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a method for forming a metal interconnection structure. Background technique [0002] When forming a metal interconnect structure (such as a copper interconnect structure), it is usually necessary to remove excess copper and barrier layers outside the trench through a chemical mechanical polishing (CMP) process until the low-K dielectric layer is polished. , exposing the metal in the trench, and forming metal wiring. [0003] At present, in the technology node of 65nm and below, due to the increasingly high requirements for the copper metal layer process, the back stage of the stack multi-layers (Line stack multi-layers) has become more complicated, usually including diffusion barrier layers, metal Hard mask layer, oxide hard mask layer and other thin film material layers, and when forming copper interconnection structure, it is necessary to grind and remove the stack of ...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768
Inventor 曹均助杨俊邵群刘洪涛钱志刚刘浩胡宗福
Owner SEMICON MFG INT (SHANGHAI) CORP