Manufacturing method for trench gate MOSFET with shield gate

Abstract

The invention discloses a manufacturing method for a trench gate MOSFET with a shield gate. The manufacturing method comprises the steps of forming a trench; forming a bottom dielectric layer formed by a first oxide film, a second nitride film and a third oxide film that are superimposed in sequence; forming a first layer of polycrystalline silicon; performing back etching on the first layer of polycrystalline silicon to form a polycrystalline silicon shield gate; forming a polycrystalline silicon isolating oxide layer by thermal oxidation; performing a first time of wet etching to remove the third oxide film in the side wall of the trench on the top of the polycrystalline silicon shield gate; performing a second time of wet etching to remove the second nitride film in the side wall of the trench on the top of the polycrystalline silicon shield gate; performing thermal oxidation on the basis of the first oxide film to form a gate oxide layer; and forming a second layer of polycrystalline silicon. According to the manufacturing method for the trench gate MOSFET with the shield gate, the void structure of the polycrystalline silicon isolating oxide layer can be eliminated, the performance of the polycrystalline silicon isolating oxide layer is improved, and the voltage resistance from the gate to the source is improved, the breakdown voltage is improved, and the current leakage is reduced.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor integrated circuit, in particular to a method for manufacturing a trench gate MOSFET with a shielding gate. Background technique [0002] like figure 1 As shown, it is a schematic structural diagram of an existing trench gate MOSFET with a shield gate (ShieldGateTrench, SGT); taking an N-type device as an example, the unit structure of an existing trench gate MOSFET with a shield gate includes: [0003] The N-type silicon epitaxial layer 102 is formed on the silicon substrate 101 . The silicon substrate 101 is heavily doped and has a drain 112 formed on the back side, and the silicon epitaxial layer 102 is lightly doped for forming a drift region. [0004] A P well 108 is formed on the surface of the silicon epitaxial layer 102 . [0005] A trench 103 enters the silicon epitaxial layer 102 through the P-well 108 , and the trench 103 is filled with a polysilicon gate 107 and a polysi...

AI Technical Summary

Problems solved by technology

According to the reliability test results, the leak point between the gate and the source (GATE-Source) at the hole is large, and it is easy to be broken down, so the existence of the hole structure will reduce the performance of the isolation oxide layer 106b between polysilicon, thereby reducing the gate To source withstand voltage Vgs, reduce breakdown voltage and increase leakage

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