Fan-out package method of embedded silicon substrate

A packaging method and a fan-out technology, which is applied in the manufacture of electrical components, electrical solid devices, semiconductor/solid devices, etc., can solve the problems of poor chip-to-panel bonding accuracy, chip position movement, and difficult alignment, etc., to achieve Effects of increasing operability and precision, improving package quality and efficiency, and reducing package cost
CN105448752AActive Publication Date: 2016-03-30HUATIAN TECH KUNSHAN ELECTRONICS
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
HUATIAN TECH KUNSHAN ELECTRONICS
Publication Date
2016-03-30

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Abstract

The invention discloses a fan-out package method of an embedded silicon substrate. The fan-out package method comprises the following steps of firstly, embedding a chip onto a silicon substrate wafer in a wafer level; secondly, laminating a plurality of silicon substrate wafers on a panel for panel level package during a fan out process; and finally, fabricating salient points or planting welding balls in the wafer level. According to the fan-out package method, the chip is embedded onto the silicon substrate wafer and then panel level package is carried out, the maneuverability and the accuracy of package are improved, and the warpage of a panel is reduced; the comprehensive alignment accuracy is improved by respective alignment adjustment on each wafer during direct laser exposure in the panel level process, so that fan-out package processing of a fine-pitch bonding pad chip is facilitated; and during the process from wafer level package to panel level package, the advantages of wide metal wiring line width, small line distance and high accuracy of wafer level package and the multiplied package quantity of the panel level package are combined, the package quality and efficiency are obviously improved, and the package cost is greatly reduced.
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Description

technical field

[0001] The invention relates to the technical field of fan-out packaging, in particular to a fan-out packaging method embedded in a silicon substrate. Background technique

[0002] As chips become smaller and the number of I / Os increases, chip-scale packaging can no longer meet the requirements of I / O fan-out. Fan-out wafer-level packaging technology (FOWLP) is a supplement to wafer-level chip size packaging technology. The chip I / O port is led out by reconfiguring the wafer, and solder balls or solder balls are formed on the reconfigured package. Bump terminal array, within a certain range, can replace the traditional wire bonding ball array (WBBGA) package or flip chip ball array (FCBGA) package (<500I / Os) package structure, especially suitable for the booming portable consumer electronics field.

[0003] Currently, there are two process routes for fan-out packaging. One is to manufacture at the wafer level, such as 8-inch or 12-inch wafers; the other...

Claims

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