Manufacturing method of trench gate power device with shield gate

Abstract

The invention discloses a manufacturing method of a trench gate power device with a shield gate. The manufacturing method comprises the following steps that: a hard mask layer is formed on the surface of a semiconductor substrate, and a gate forming region is defined on the surface of the semiconductor substrate through photoetching; first anisotropic etching is performed on the semiconductor substrate at the gate forming region, so that trenches can be formed, and the width of the trenches is expanded to a width larger than an opening width defined by the hard mask layer through second isotropic etching; a gate dielectric layer and a polysilicon gate are formed; back etching is performed on the polysilicon gate; with the hard mask layer adopted as a mask, third isotropic etching is performed on the semiconductor substrate at the bottoms of the trenches, so that deep trenches can be formed; a first oxide layer is formed at the side surfaces and bottom surfaces of the deep trenches as well as the side surfaces of the polysilicon gate simultaneously; and source polysilicon is grown. With the manufacturing method of the invention adopted, the polysilicon gate of a sidewall polysilicon structure can be formed, and the thickness of a gate and source isolation oxide layer can be improved, and gate and source electric leakage can be decreased.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor integrated circuit, in particular to a method for manufacturing a trench gate power device with a shield gate (ShieldGateTrench, SGT). Background technique [0002] Such as Figure 1A to Figure 1F Shown is a schematic diagram of the device structure in each step of the existing manufacturing method of a trench gate power device with a shielded gate; this method is to use a bottom-up method to form a trench gate structure with a shielded gate, including the following steps : [0003] Step 1, such as Figure 1A As shown, a semiconductor substrate such as a silicon substrate 101 is provided; a hard mask layer 102 is formed on the surface of the semiconductor substrate 101, and the hard mask layer 102 can be an oxide layer, or an oxide layer plus a nitride layer. Afterwards, the hard mask layer 102 is etched by photolithography to define a gate formation region, and then the semiconducto...

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Problems solved by technology

However, in the above-mentioned existing method, the oxide layer isolated between the other side of the polysilicon gate 106 and the source polysilicon 105, that is, the gate-source isolation oxide layer is formed simultaneously with the gate oxide layer, which makes the gate-source isolation oxide layer and the gate oxide layer layer is as thin as the

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