Directional growth copper pillar bump interconnection structure and preparation method thereof

A technology of interconnection structure and directional growth, applied in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., to achieve the effect of improving interconnection performance and service reliability, realizing industrialization, and easy industrialization

Active Publication Date: 2018-04-24
INST OF METAL RESEARCH - CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] However, the existing nano-twinned copper preparation technology mainly uses a Ti plate or an amorphous Ni-P film as a cathode plate to prepare a nano-twinned copper bulk material that can be peeled off, which is different from the wafer-based substrate in the microelectronics industry. The process for electroplating is very different, and there is no case of using this high-performance nano-twinned copper in the microelectronics industry

Method used

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  • Directional growth copper pillar bump interconnection structure and preparation method thereof
  • Directional growth copper pillar bump interconnection structure and preparation method thereof
  • Directional growth copper pillar bump interconnection structure and preparation method thereof

Examples

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Embodiment 1

[0054] figure 2 It is a process flow chart for preparing a copper pillar bump interconnection structure of directional growth nano-twinned copper in the present invention, and the process steps are:

[0055] (1) Prepare the wafer substrate 1 with insulating layer 2, such as figure 2 (a), arranging a metal disc 4 on the insulating layer 2; or directly using a chip on which a metal disc and interconnection lines have been arranged as a substrate;

[0056] (2) deposit dielectric layer 3 on insulating layer 2 and metal plate 4, as figure 2 (b), selectively masking and etching the dielectric layer makes the surface of the metal disk 4 exposed in the window of the dielectric layer 3, such as figure 2 (c);

[0057] (3) Deposit seed layer 5 on dielectric layer 3 and exposed metal disk 4, as figure 2 (d); The method of depositing the seed layer is physical vapor deposition (PVD) or sputtering, etc., the thickness of the seed layer is about 200nm, and the materials are Ti and C...

Embodiment 2

[0068] This embodiment is a preparation process for a copper pillar bump interconnection structure of directional growth nano-twinned copper, which is different from Embodiment 1 in that: step (5) in the process of direct current electroplating copper pillars: the electroplating solution is composed of: copper sulfate 200g / L, methanesulfonic acid 40mL / L, sodium chloride 30ppm (calculated according to the chlorine content in sodium chloride), polyethyleneimine 5ppm, gelatin 20ppm, and the rest is water; the electroplating anode plate is phosphor copper plate, phosphor copper plate The P element content in the medium is 0.03‐0.075wt.%, and the current density is 40mA / cm 2 , Electromagnetic stirring is used in the electroplating process to ensure that the concentration in the plating solution is uniform.

[0069] The cross-sectional structure of the copper pillars in the copper pillar bump interconnection structure obtained in this embodiment is analyzed, and the result is the sa...

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Abstract

The invention discloses a directional growth copper pillar bump interconnection structure and a preparation method thereof, belonging to the field of packaging of microelectronics and microelectromechanical systems. The copper pillar bump interconnection structure includes a wafer substrate, an insulating layer, a metal disc, a dielectric layer, a seed layer, a copper pillar and a solder bump, and the copper pillar contains a nano-twinned copper structure oriented growth; the copper pillar The top end features a solder bump. The present invention utilizes the traditional DC electroplating process to prepare a copper pillar bump interconnection structure containing directional growth nano-twinned copper on the wafer substrate. On the other hand, because the DC electroplating process is compatible with the existing wafer-level packaging technology, it is easier to realize the industrialization of the invention.

Description

technical field [0001] The present invention relates to the technical field of packaging of microelectronics and micro-electromechanical systems, in particular to a directional growth copper pillar bump interconnection structure and a preparation method thereof, which prepares directional growth copper pillar bumps on a wafer substrate based on direct current electroplating technology interconnect structure. The method can be applied to the copper pillar bump technology using the copper filling process in the wafer level packaging process. Background technique [0002] In recent years, in the field of microelectronic interconnection, common packaging forms are SIP, CSP or BGA. These packaging technologies have been widely used in computers, mobile phones, and memory devices, but the rapidly developing electronics industry has been seeking a packaging structure that can achieve higher density interconnection in a smaller size. Therefore, copper pillar bump technology and ho...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/48H01L23/488H01L21/768
CPCH01L2224/11H01L2224/13147
Inventor 刘志权孙福龙李财富祝清省郭敬东
Owner INST OF METAL RESEARCH - CHINESE ACAD OF SCI
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