Ferro-electric field effect transistor based on InAs material and preparation method of ferro-electric field effect transistor

Abstract

The invention relates to a ferro-electric field effect transistor based on an InAs material and a preparation method of the ferro-electric field effect transistor, which are used for solving the problems that conductive current of a traditional Si-Based ferro-electric field effect transistor is small and sub-threshold swing cannot be reduced. The transistor comprises a substrate 1, a source 2, a channel 3, a drain 4, an insulation dielectric thin film 5, an internal grid electrode 6, a ferro-electric grid dielectric layer 7 and a grid electrode 8, wherein the channel 3 is arranged at a central position of the upper part of the substrate 1, the source 3 and the drain 4 are arranged on the two sides of the cahnnel 3, and the insulation dielectric thin film 5, the internal grid electrode 6, the ferro-electric dielectric layer 7 and the grid electrode 8 are sequentially and vertically arranged on the channel 3 from bottom to top. The InAs material is introduced to the field effect transistor and serves as a channel material of the transistor, so that the transistor can acquire relatively low sub-threshold swing and relatively high switching speed on the condition of relatively low working voltage.

Description

technical field [0001] The invention belongs to the technical field of electronics, and further relates to a ferroelectric field-effect transistor based on InAs material in the technical field of microelectronic devices and a preparation method thereof. The invention can be used in large-scale integrated circuits with high performance and low power consumption. Background technique [0002] With the development of integrated circuits, the feature size of chips has been continuously reduced, and the integration level on a single chip has increased accordingly, and the resulting power consumption problem has become more and more serious. According to ITRS data, when the feature size is reduced to the 32nm node, the power consumption will be 8 times the expected trend, that is, with the gradual reduction of the feature size, traditional MOS devices will not be able to meet the performance requirements in terms of power consumption. In addition, the reduction of MOSFET size is ...

AI Technical Summary

Problems solved by technology

However, the disadvantage of the MFIS-FET structure is that the electron mobility of silicon, the material used for the substrate, is low, which leads to a small conduction current of the transistor, and it becomes difficult to further reduce the subthreshold swing. Therefore, the switching speed of the transistor cannot be increased, the power consumption of the transistor can be reduced, and the application requirements of high-performance devices cannot be met.

However, there are still deficiencies that the ferroelectric field effect transistor of the regular carbon nanotube stripe array cannot reduce the operating voltage while increasing the transistor conduction current, resulting in high power consumption of the transistor; and cannot reduce the subthreshold swing Amplitude, to further increase the switching speed of transistors, cannot meet the manufacturing requirements of high-speed, low-power large-scale integrated circuits

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