Method to improve sonos memory read operation capability

Abstract

The invention discloses a method for improving SONOS memory reading operation capability. The method comprises steps that N-type light doping drain injection is carried out after formation of a grid electrode; a silicon nitride side wall is formed; a silicon dioxide layer for source and drain injection protection is formed at a front face of a silicon substrate; an NPC-level light cover is employed to from a first photoresist graph to define contact hole opening zones between grid electrodes of an SONOS transistor and an N-type transistor; the first photoresist graph is utilized as a mask layer for respectively etching the silicon dioxide layer and the silicon nitride side wall; source and drain injection is carried out. Through the method, the reading current of devices can be improved, and reading operation capability of the devices is improved.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit manufacturing method, in particular to a method for improving the reading operation capability of SONOS memory. Background technique [0002] SONOS (Silicon-Silicon Oxide-Silicon Nitride-Silicon Oxide-Silicon) flash memory device has become one of the main flash memory device types at present because of its good scaling characteristics and radiation resistance characteristics. [0003] The cell structure of the existing SONOS memory consists of a SONOS transistor and a transfer transistor, such as figure 1 As shown, it is a schematic diagram of the structure of the existing SONOS memory cell; the area shown by the dotted line 103 is a SONOS transistor, the area shown by the dotted line 104 is a transfer transistor, and a P well 102 is formed on the surface of the silicon substrate 101, and the gate of the SONOS transistor The structure is composed of stacked ONO layer 105a and polysilicon gat...

AI Technical Summary

Problems solved by technology

[0004] The SONOS transistor is used to store and store the working state, that is, 0 or 1, and the transfer transistor is responsible for transmitting the stored working state; when the structure of the SONOS transistor shrinks, the gap D1 between the SONOS transistor and the transfer transistor gradually decreases, forming a gate After the sidewall, the gap D1 between the SONOS transistor and the transfer transistor is further reduced, for example, to 0.15 microns, and a layer needs to be grown before the source-drain injection Silicon dioxide 108 on the left and right, so that the gap between the SONOS transistor and the transfer transistor is filled with silicon dioxide 108, so that the gap between the SONOS transistor and the transfer transistor is due to two Blocked by the filling of silicon oxide 108, only a small amount of source and drain ions are implanted into the silicon substrate 101, that is, the junction depth and doping concentration of the finally formed source and drain regions 109c will be smaller than those of the source and drain regions 109a and 109b, which will Detrimentally affects the current flow of the SONOS transistor and the pass transistor, thereby adversely affecting the read operation of the circuit

Therefore, as the size of the cell structure of the SONOS memory continues to decrease, the read current of the SONOS memory formed by the existing method will decrease, and the read operation capability will decrease.

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