Semiconductor device and manufacturing method thereof, and electronic device

Abstract

The invention relates to a semiconductor device, a manufacturing method thereof, and an electronic device. The method includes step S1: providing a semiconductor substrate, on which a doped oxide layer is formed, and a number of dummy nuclei arranged at intervals are formed on the doped oxide layer; step S2: Depositing a layer of spacer material to cover the dummy core and the semiconductor substrate; step S3: choose CF 3 I and H 2 Etching the spacer material layer to form a spacer on the sidewall of the dummy core; step S4: removing the dummy core to obtain a fin pattern. The advantage of the present invention is that the preparation method of the double pattern is more robust, and the prepared FinFET has better performance and yield.

Description

Technical field [0001] The present invention relates to the field of semiconductor manufacturing. Specifically, the present invention relates to a semiconductor device, a manufacturing method thereof, and an electronic device. Background technique [0002] The improvement of integrated circuit performance is mainly achieved by continuously reducing the size of integrated circuit devices to increase its speed. At present, as the semiconductor industry pursuing high device density, high performance, and low cost has developed to smaller technology process nodes, challenges from manufacturing and design have promoted the development of three-dimensional designs such as FinFETs. [0003] Compared with the existing planar transistors, FinFET devices have more superior performance in channel control and reduction of shallow channel effects; among them, the planar gate structure is arranged above the channel, and the gate in FinFET Surrounding the fins can control static electricity from...

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Problems solved by technology

[0007] Among them, the spacer is widely used in self-aligned double patterning (Self-aligned double patterning, SADP), usually using lithography-etch-film deposition-etch-removal-nucleus-etch (Litho–Etch–filmdeposition-Etch–Strip -Etch.) method to prepare a semiconductor device, such as selecting amorphous carbon A-C and patterning it as the core (core) in the double pattern, then selecting a low-temperature deposition method to form a spacer layer on the A-C, and finally removing the A-C core, the method usually forms a cone-shaped core and also causes a burden when the dielectric anti-reflective coating (dielectric Anti-reflectivecoating, DRAC) is covered. In addition, there are odd-even (Even-odd) problems, such as odd-even critical dimensions Insufficient uniformity (Even-odd CDloading), in the prior art usually select polysilicon to replace described A-C to prepare polysilicon core, but polysilicon is easy to be oxidized in the preparation process, can cause odd-even number (Even-odd) problem likewise, make final The critical dimensions of the prepared fins are not uniform enough

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