Method of forming semiconductor device

Abstract

The invention provides a semiconductor device forming method. The method comprises steps: a substrate with a first area and a second area is provided, a first pseudo gate is formed on part of the substrate in the first area, a second metal gate is formed on part of the substrate in the second area, an interlayer dielectric layer is also formed on the surface of the substrate in the first area and in the second area, and the interlayer dielectric layer coats the side wall surface of the first pseudo gate and the side wall surface of the second metal gate; a synchronous pulse etching process is adopted to etch and remove the first pseudo gate, and a first opening is formed in the interlayer dielectric layer in the first area; a synchronous pulse method is adopted to carry out etching post-treatment on the first opening, and the treatment gas for the etching post-treatment comprises a carbon tetrafluoride gas; and a first metal gate filling the first opening is formed. The etched and removed thickness of the interlayer dielectric layer is small, the etched and removed thicknesses of the interlayer dielectric layer in a graph sparse area and a graph intensive area are consistent, and the electrical performance of the semiconductor device is thus improved.

Description

technical field [0001] The invention relates to the technology in the field of semiconductor manufacturing, in particular to a method for forming a semiconductor device. Background technique [0002] At present, in the manufacturing process of semiconductor devices, a P-type metal oxide semiconductor (PMOS, P type Metal Oxide Semiconductor) tube, an N-type metal oxide semiconductor (NMOS, N type Metal Oxide Semiconductor) tube, or a combination of a PMOS tube and an NMOS tube The formed Complementary Metal Oxide Semiconductor (CMOS, Complementary Metal Oxide Semiconductor) tube is the main device constituting the chip. [0003] With the continuous development of integrated circuit manufacturing technology, the technology nodes of semiconductor devices are continuously reduced, and the geometric dimensions of devices are continuously reduced following Moore's law. When the device size is reduced to a certain extent, various secondary effects caused by the physical limit of t...

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Problems solved by technology

[0005] The problem solved by the present invention is that in the process of forming the second metal gate first and then the first metal gate, the loss of the interlayer dielectric layer is too much, resulting in low electrical performance of the formed semiconductor device

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