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Method for manufacturing trench gate power devices with shielded gate

A technology of power devices and manufacturing methods, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems affecting device threshold voltage, poor quality of thermal silicon oxide, etc., achieve pitch reduction, strong filling ability, and trench Effect of slot width reduction

Inactive Publication Date: 2016-09-21
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the quality of thermal silicon oxide grown on polysilicon is relatively poor, and a sufficiently thick isolation silicon oxide must be obtained by increasing the thickness of the gate silicon oxide; this will affect the threshold voltage (VT) of the device and the switching process of the unclamped inductive load. switching, UIS) capability

Method used

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  • Method for manufacturing trench gate power devices with shielded gate
  • Method for manufacturing trench gate power devices with shielded gate
  • Method for manufacturing trench gate power devices with shielded gate

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Embodiment Construction

[0046] Such as image 3 Shown is the flow chart of the method of the embodiment of the present invention; Figure 4A to Figure 4O Shown is a schematic diagram of the device structure in each step of the method of the embodiment of the present invention. The manufacturing method of the trench gate power device with the shield gate 4 in the embodiment of the present invention includes the following steps:

[0047] Step 1, such as Figure 4A As shown, a silicon substrate 1 is provided, and a groove 303 is formed in the silicon substrate 1 by photolithography.

[0048] Preferably, a silicon epitaxial layer 2 is formed on the surface of the silicon substrate 1 , and the trench 303 is formed in the silicon epitaxial layer 2 .

[0049] Forming the trench 303 includes the following sub-steps:

[0050] Such as Figure 4B As shown, a hard mask layer 301 is formed on the surface of the silicon substrate 1 . The hard mask layer 301 is composed of an oxide layer or an oxide layer plu...

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Abstract

The invention discloses a method for manufacturing a trench gate power device with a shield gate, which comprises the following steps: step 1, providing a silicon substrate and forming a trench in the silicon substrate; step 2, forming a trench at the bottom of the trench The first silicon oxide layer and the shield gate; Step 3, forming a second silicon oxide layer; Step 4, depositing a BPSG film and performing reflow planarization, and completely filling the top of the trench with the BPSG film and the second silicon oxide layer; Step 5 1. Etching back the silicon oxide to form an isolation dielectric layer between polysilicon composed of the etched back BPSG film and the second silicon oxide layer; step 6, forming a gate dielectric layer and a polysilicon gate on the top of the trench. The invention can reduce the unit structure size of the device and obtain a thin grid dielectric layer, thereby reducing the conduction voltage drop of the device and realizing low-voltage application.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor integrated circuit, in particular to a method for manufacturing a trench gate power device with a shield gate (Shield Gate Trench, SGT). Background technique [0002] A trench gate power device with a shield gate needs to form a shield gate at the bottom of the trench gate. The shield gate and the trench gate are generally composed of polysilicon, and the shield gate and the trench gate need to be isolated by an isolation dielectric layer between polysilicon . In the existing method, there are two methods for forming the isolation dielectric layer between polysilicon. The first method is to deposit silicon oxide to fill the top of the shield gate after the shield gate is formed. trenches, and then silicon oxide is etched back to form an isolation dielectric layer between polysilicon; the second method is to form an isolation dielectric layer between polysilicon by using a thermal oxid...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L21/28H01L29/06H01L29/423
CPCH01L29/66666H01L29/0649H01L29/42364
Inventor 柯行飞
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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