Hole current shunting type power transistor with high avalanche tolerance and preparation method thereof

Abstract

A hole-current shunt power transistor with high avalanche tolerance and a preparation method thereof, comprising: an N-type doped silicon epitaxial layer is arranged on an N-type doped silicon substrate serving as a drain region, and an N-type doped silicon epitaxial layer is provided. Grooves are arranged on the surface, and a field oxygen layer is arranged in the groove, and a shielding gate and a gate are arranged in the field oxygen layer. The gate is located on both sides of the shielding gate and on the top of the field oxygen layer. An insulating dielectric layer is provided between them, and at the same time, a gate oxide layer is provided between the gate and the epitaxial layer, a P-type body region is provided on the surface of the epitaxial layer, and a P-type source region and an N-type body region are provided on the surface of the P-type body region. The source area, the surface of the device is covered with an insulating dielectric layer, the source metal is in contact with the heavily doped N-type source area and the heavily doped P-type source area through the through hole on the insulating dielectric layer, the shielding gate is also in contact with the source metal, and the oxygen in the field A P-type polysilicon conduction channel located under the gate is arranged in the layer, one end of the P-type polysilicon conduction channel is connected to the N-type doped silicon epitaxial layer, and the other end is connected to the shielding grid.

Description

technical field [0001] The invention belongs to the technical field of semiconductor power devices, and relates to a power semiconductor transistor with high avalanche tolerance and a preparation method thereof, and is especially suitable for electric vehicles, motor speed regulation, inverters, uninterruptible power supplies, electronic switches, high-fidelity audio, and automobiles. Electrical and electronic rectifiers. Background technique [0002] As a deep trench metal oxide semiconductor field effect transistor, the shielded gate field effect transistor has a small on-resistance, and has a smaller Miller capacitance than the traditional deep trench metal oxide semiconductor field effect transistor, so Its switching speed is significantly improved, and the turn-off loss is significantly reduced. Therefore, shielded gate field effect transistors are widely used, and can be applied to motor speed regulation, inverters, uninterruptible power supplies, electronic switches, ...

AI Technical Summary

Problems solved by technology

One of the main factors causing the low avalanche tolerance of the device is that the parasitic triode is turned on prematurely. The reason why the parasitic triode is turned on prematurely is because the device is in the state of avalanche breakdown and must withstand high voltage and large current, the power of the device is large, and the temperature rises rapidly , causing the base resistance of the parasitic triode to increase rapidly, at this time a large amount of avalanche current flows through the base resistance of the parasitic triode, the base-emitter potential difference increases rapidly, and finally the parasitic triode turns on prematurely

[0004] In order to suppress the opening of the parasitic triode and improve the avalanche tolerance of the device, the current common practice is to reduce the density of the avalanche current by increasing the area of ​​the device, but the manufacturing cost of the device increases; or change the area related to the avalanche tolerance in the device The doping concentration can reduce the base resistance of the parasitic transistor, which can theoretically improve the avalanche resistance, but the effect is not obvious; or increase the depth of the contact hole to reduce the base resistance of the parasitic transistor, but the effect is also not obvious

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