Preparation method of TFT substrate and TFT substrate
A substrate and transparent substrate technology, used in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of TFT glass substrates that are not resistant to high temperature, affect structural stability, and improve product yield, and achieve high quality The effect of easy control, improved production efficiency and low production cost
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Embodiment 1
[0066] Such as Figure 4-19b Shown, a kind of preparation method of TFT substrate comprises the steps:
[0067] S1: Depositing a gate metal layer 2 , a gate insulating layer 3 , a semiconductor layer 5 and a source / drain metal layer 5 on a transparent substrate 1 in sequence.
[0068] The material of the gate metal layer 2 and the source / drain metal layer 5 in this step is preferably but not limited to Al, Cu, Mo or Cr, etc., and the material of the gate insulating layer 3 is preferably but not limited to silicon nitride, silicon oxide or nitrogen Silicon oxide or the like, the material of the semiconductor layer 5 is preferably but not limited to single crystal silicon, polycrystalline silicon, or amorphous silicon.
[0069] S2: Coating the first photoresist 8 on the source / drain metal layer 5, performing masking and etching to form the data line 22, the gate line 23, the gate electrode 21, the gate insulating layer 3, and the semiconductor channel 41 , source electrode 52 ...
Embodiment 2
[0098] Such as Figure 1-3 As shown, a TFT substrate includes a plurality of pixel units, and each pixel unit includes a gate metal layer 2, a gate insulating layer 3, a semiconductor layer 5, a source / drain metal layer 5, and an insulating medium sequentially formed on a transparent substrate 1. layer 6 and pixel electrode layer 7, wherein:
[0099] The gate metal layer 2 includes a gate electrode 21, a horizontal gate line 23 and a vertical data line 22, the gate electrode 21 is connected to the gate line 23, and the data line 22 is disconnected from the gate electrode 21 and the gate line 23 ;
[0100] The gate insulating layer 3 is located on the gate electrode 21 and the gate line 23, and is used to insulate the gate line 23 / gate electrode 21 from the source electrode 52 / drain electrode 51;
[0101] The semiconductor layer 5 is located on the gate insulating layer 3 of the gate electrode 21, and a semiconductor channel 41 is formed thereon;
[0102] The source / drain me...
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